Problems with resolved types and multiple drivers

[Markus Jochim]

Hello,
I'm just starting with VHDL and encountered a problem with "resolved
types" and "multiple drivers".

The following code does not work.

Altera Quartus II Web Edition says:
"Can't resolve multiple constant drivers for net "0.'0'" at cnt.vhd(57)"
and complains about the line O <= tmp1;

Xilinx ISE9.1i says:
ERROR:Xst:800 - "C:/Programme/Xilinx91i/Versuch/cnt.vhd" line 58:
Multi-source on Integers in Concurrent Assignment.
and complains about the line O <= tmp2;

I'm sure that both tools know much more about VHDL then I do ;-)

According to my understanding the code should work since I use a
resolved type.

Can anyone help me with this question which is probably a real
"Newbie-Question"... I just can't find a solution in my books and tutorials.

By the way: I'm not looking for a workaround or something... I just want
to understand the problem!

Thanks in advance

Markus



package types is
type xbit is ( '0', -- Logical 0
'1', -- Logical 1
'X', -- Unknown
'Z' -- High Impedance
);

type xbit_vector is array ( natural range <> ) of xbit;

function resolve_xbit ( v : xbit_vector ) return xbit;

subtype xbit_resolved is resolve_xbit xbit;
end types;


package body types is
type xbit_table is array(xbit, xbit) of xbit;
constant resolution_table: xbit_table := (
-- 0 1 X Z
( '0', 'X', 'X', '0' ), -- 0
( 'X', '1', 'X', '1' ), -- 1
( 'X', 'X', 'X', 'X' ), -- X
( '0', '1', 'X', 'Z' ) -- Z
);

function resolve_xbit ( v: xbit_vector ) return xbit is
variable result: xbit;
begin
-- test for single driver
if (v'length = 1) then
result := v(v'low); -- Return the same value if only 1 value
else
result := 'Z';
for i in v'range loop
result := resolution_table(result, v(i));
end loop;
end if;
return result;
end resolve_xbit;
end types;



use work.types.all;
entity threestate is
port (en1, en2: in xbit_resolved;
A,B: in xbit_resolved;
O: out xbit_resolved);
end threestate;


architecture sample of threestate is
signal tmp1,tmp2: xbit_resolved;
begin
tmp1 <= A when en1 = '1' else 'Z';
tmp2 <= B when en2 = '1' else 'Z';
O <= tmp1;
O <= tmp2;
end sample;

 

[Mike Treseler]

I'm just starting with VHDL and encountered a problem with "resolved
types" and "multiple drivers".

Writing new resolved types and associated
functions is not something
that most designers would take on willingly
given this work has already been done for std_logic.

The following code does not work.

Altera Quartus II Web Edition says:
"Can't resolve multiple constant drivers for net "0.'0'" at cnt.vhd(57)"
and complains about the line O <= tmp1;

Learn simulation.
Post a testbench that demonstrates the problem.

Can anyone help me with this question which is probably a real
"Newbie-Question"... I just can't find a solution in my books and tutorials.

This is an advanced topic, not needed
for ordinary design work.
It would be out of place in a tutorial.
Consider revisiting this topic later.

-- Mike Treseler

 

[Paul Uiterlinden]

Hello,
I'm just starting with VHDL and encountered a problem with "resolved
types" and "multiple drivers".

The following code does not work.

Altera Quartus II Web Edition says:
"Can't resolve multiple constant drivers for net "0.'0'" at cnt.vhd(57)"
and complains about the line O <= tmp1;

Xilinx ISE9.1i says:
ERROR:Xst:800 - "C:/Programme/Xilinx91i/Versuch/cnt.vhd" line 58:
Multi-source on Integers in Concurrent Assignment.
and complains about the line O <= tmp2;

I'm sure that both tools know much more about VHDL then I do ;-)

According to my understanding the code should work since I use a
resolved type.

Though I have not simulated your code, I think it should work. In
simulation, that is. Synthesis is another matter. I suspect (but I'm not
sure, I hardly use any synthesizer) that synthesizers do not allow you to
write custom resolution functions.

By the way: I'm not looking for a workaround or something... I just want
to understand the problem!

First step is simulate.

 

[palo]

hej.
I'm new here and I'm just reading everything there is about VHDL since I'm taking a course that deals with it at my university. I have a question about these two lines:

function resolve_xbit ( v : xbit_vector ) return xbit;

subtype xbit_resolved is resolve_xbit xbit;

especially the second one after the word 'is'. How does the subtype declaration work with the function in this case?

and another thing - how should this xbit_resolved type deal with the multiple drivers in the architecture? I mean what should be the result of this code if there are two drivers driving the O signal?

Sorry for such basic questions but I'm only starting to get acquainted with the language

 

[Martin Thompson]

Hello,
I'm just starting with VHDL and encountered a problem with "resolved
types" and "multiple drivers".

The following code does not work.

Altera Quartus II Web Edition says:
"Can't resolve multiple constant drivers for net "0.'0'" at cnt.vhd(57)"
and complains about the line O <= tmp1;

Xilinx ISE9.1i says:
ERROR:Xst:800 - "C:/Programme/Xilinx91i/Versuch/cnt.vhd" line 58:
Multi-source on Integers in Concurrent Assignment.
and complains about the line O <= tmp2;

I'm sure that both tools know much more about VHDL then I do ;-)

According to my understanding the code should work since I use a
resolved type.

Can anyone help me with this question which is probably a real
"Newbie-Question"... I just can't find a solution in my books and tutorials.

By the way: I'm not looking for a workaround or something... I just want
to understand the problem!

The problem is that synthesisers (that I know of) only understand the
resolutions of std_(u)logic types. Creating your own resolved type is
fine for simulations, but you won't be able to synthesise it.

Cheers,
Martin

 

[Andy]

Hello,
I'm just starting with VHDL and encountered a problem with "resolved
types" and "multiple drivers".

The following code does not work.

Altera Quartus II Web Edition says:
"Can't resolve multiple constant drivers for net "0.'0'" at cnt.vhd(57)"
and complains about the line O <= tmp1;

Xilinx ISE9.1i says:
ERROR:Xst:800 - "C:/Programme/Xilinx91i/Versuch/cnt.vhd" line 58:
Multi-source on Integers in Concurrent Assignment.
and complains about the line O <= tmp2;

I'm sure that both tools know much more about VHDL then I do ;-)

According to my understanding the code should work since I use a
resolved type.

Can anyone help me with this question which is probably a real
"Newbie-Question"... I just can't find a solution in my books and tutorials.

By the way: I'm not looking for a workaround or something... I just want
to understand the problem!

Thanks in advance

Markus

package types is
type xbit is ( '0', -- Logical 0
'1', -- Logical 1
'X', -- Unknown
'Z' -- High Impedance
);

type xbit_vector is array ( natural range <> ) of xbit;

function resolve_xbit ( v : xbit_vector ) return xbit;

subtype xbit_resolved is resolve_xbit xbit;
end types;

package body types is
type xbit_table is array(xbit, xbit) of xbit;
constant resolution_table: xbit_table := (
-- 0 1 X Z
( '0', 'X', 'X', '0' ), -- 0
( 'X', '1', 'X', '1' ), -- 1
( 'X', 'X', 'X', 'X' ), -- X
( '0', '1', 'X', 'Z' ) -- Z
);

function resolve_xbit ( v: xbit_vector ) return xbit is
variable result: xbit;
begin
-- test for single driver
if (v'length = 1) then
result := v(v'low); -- Return the same value if only 1 value
else
result := 'Z';
for i in v'range loop
result := resolution_table(result, v(i));
end loop;
end if;
return result;
end resolve_xbit;
end types;

use work.types.all;
entity threestate is
port (en1, en2: in xbit_resolved;
A,B: in xbit_resolved;
O: out xbit_resolved);
end threestate;

architecture sample of threestate is
signal tmp1,tmp2: xbit_resolved;
begin
tmp1 <= A when en1 = '1' else 'Z';
tmp2 <= B when en2 = '1' else 'Z';
O <= tmp1;
O <= tmp2;
end sample;

Synthesis tools do not generally accept arbitrary scalar signal types.
The tool's documentation will list what types are supported, and with
the exception of enumerated types for state machines, user-defined
scalar types are not supported. Typically types from std,
std_logic_1164, numeric_std, numeric_bit, and user defined composites
of those types are supported by synthesis tools. User defined
resolution functions are generally not supported.

However, simulators generally support anything that is legal per the
DRM. This can be useful for behavioral modeling and testbenches.

Andy