M
Michel Bieleveld
Hi All,
I have a problem, as far as I know procedures can change
signals/variables as long as the procedures are defined within the
scope where the variables are defined. Yet when i try to simulate my
vhdl code the ISE synthesizer gives me the following warning :
WARNING:Xst:1960 - C:/projects/redemption/ax88796.vhd line 86:
Potential simulation mismatch, variable <register_uit> declared in
block <$PROCESS1> is assigned in block <WriteReg>.
My code looks basicly like the code shown here. It seems like that the
variables within the procedure do not change the variable outside the
procedure, which is what i was hoping for.
Is there any Macro command or something in vhdl, because that is what
i am using the procedure for.
With regards,
Michel Bieleveld.
entity ax88796 is
...
end ax88796;
architecture RTL of ax88796 is
...
begin
process (nRST,CLK)
...
variable operand : std_logic_vector(15 downto 0);
procedure ReadReg(Ax_reg : in std_logic_vector(7 downto 0))is
begin
operand := B"00001110" & Ax_reg;
return_state := current_state;
next_state := st_ExRead;
end ReadReg;
begin
...
blahblah ReadReg(X"00");
...
end process;
end rtl;
I have a problem, as far as I know procedures can change
signals/variables as long as the procedures are defined within the
scope where the variables are defined. Yet when i try to simulate my
vhdl code the ISE synthesizer gives me the following warning :
WARNING:Xst:1960 - C:/projects/redemption/ax88796.vhd line 86:
Potential simulation mismatch, variable <register_uit> declared in
block <$PROCESS1> is assigned in block <WriteReg>.
My code looks basicly like the code shown here. It seems like that the
variables within the procedure do not change the variable outside the
procedure, which is what i was hoping for.
Is there any Macro command or something in vhdl, because that is what
i am using the procedure for.
With regards,
Michel Bieleveld.
entity ax88796 is
...
end ax88796;
architecture RTL of ax88796 is
...
begin
process (nRST,CLK)
...
variable operand : std_logic_vector(15 downto 0);
procedure ReadReg(Ax_reg : in std_logic_vector(7 downto 0))is
begin
operand := B"00001110" & Ax_reg;
return_state := current_state;
next_state := st_ExRead;
end ReadReg;
begin
...
blahblah ReadReg(X"00");
...
end process;
end rtl;