D
Duke Scarring
Hi folks,
I want process all elements of an unknown vhdl record. The following way
did'nt work with vhdl:
--
type r_t is record
a : std_logic;
b : bit_vector(3 downto 0);
i : integer;
end record;
dont_go: process
variable v : r_t;
begin
for i in v'range loop
do_something( v.i );
end loop;
end process;
--
With this way it works, but if I enhance my record, I also have to
enhance the process:
--
is_ok: process
variable v : r_t;
begin
do_something( v.a);
do_something( v.b);
do_something( v.i);
end process;
--
Maybe anyone has an suggestion how to handle such thing sophisticated
and flexible.
Thanks,
Duke
I want process all elements of an unknown vhdl record. The following way
did'nt work with vhdl:
--
type r_t is record
a : std_logic;
b : bit_vector(3 downto 0);
i : integer;
end record;
dont_go: process
variable v : r_t;
begin
for i in v'range loop
do_something( v.i );
end loop;
end process;
--
With this way it works, but if I enhance my record, I also have to
enhance the process:
--
is_ok: process
variable v : r_t;
begin
do_something( v.a);
do_something( v.b);
do_something( v.i);
end process;
--
Maybe anyone has an suggestion how to handle such thing sophisticated
and flexible.
Thanks,
Duke