PSL tutotorial at designcon and dvcon

[ben cohen]

I wonder whether there's a way to speed the design process up.

Maybe the integration of PSL into VHDL (and other languages) can help here.
You still need simulation but you can include properties in your design.
See: http://www.accellera.org
Ben Cohen has written a book "Using PSL/Sugar with Verilog and VHDL".
Egbert Molenkamp

I'll be giving at designcon and dvcon a 3-hour tutorial on "Using PSL/Sugar for
Static and Dynamic Verification". That tutorial will be based on my
upcoming book (in late January) "Using PSL/Sugar with HDL for Formal
and Dynamic Verification 2nd Edition", authored by Ben Cohen,
Srinivasan Venkataramanan and Ajeetha Kumari.
http://www.designcon.com/conference/schedule.html
http://www.dvcon.com/tutorials.html
----------------------------------------------------------------------------
Ben Cohen Publisher, Trainer, Consultant (310) 721-4830
http://www.vhdlcohen.com/ (e-mail address removed)
Author of following textbooks:
* Using PSL/SUGAR with Verilog and VHDL
Guide to Property Specification Language for ABV, 2003 isbn 0-9705394-4-4
* Real Chip Design and Verification Using Verilog and VHDL, 2002 isbn 0-9705394-2-8
* Component Design by Example ", 2001 isbn 0-9705394-0-1
* VHDL Coding Styles and Methodologies, 2nd Edition, 1999 isbn 0-7923-8474-1
* VHDL Answers to Frequently Asked Questions, 2nd Edition, isbn 0-7923-8115
------------------------------------------------------------------------------

 

[Srinivasan Venkataramanan]

Hi,


If the verification is done in a hierarchical fashion, then Formal
Verifcation (Model Checking) is an option too, and many FV tools support PSL
as of today. That would mean that to start with you don't need to build
complex testbenches, write your design, specifiy the design properties using
PSL and use FV. Our upcoming book (referred to by Ben) will address this
aspect as well.

Regards,
Srinivasan

<SNIP>

--
Srinivasan Venkataramanan
Senior Verification Engineer
Software & Silicon Systems India Pvt Ltd. - an Intel company
Bangalore, India

http://www.noveldv.com http://www.deeps.org

I don't speak for Intel

 

[annytom]

hdj

Hi,



If the verification is done in a hierarchical fashion, then Formal
Verifcation (Model Checking) is an option too, and many FV tools support PSL
as of today. That would mean that to start with you don't need to build
complex testbenches, write your design, specifiy the design properties using
PSL and use FV. Our upcoming book (referred to by Ben) will address this
aspect as well.

Regards,
Srinivasan



--
Srinivasan Venkataramanan
Senior Verification Engineer
Software & Silicon Systems India Pvt Ltd. - an Intel company
Bangalore, India

http://www.noveldv.com http://www.deeps.org

I don't speak for Intel