Purpose of a string variable in a FSM process

[a s]

Hello,

I am working with Xilinx tools and have troubles understanding the
purpose
of a string variable init_fsm_name in the FSM process posted below
(snipped).
The code below was generated by Xilinx Core Generator.

I guess it must be related to simulation, but simulation tools can
already
extract the name from the FSM state init_state_r.

I would be grateful for shedding a light regarding this question.

process (pma_reset_done_i, init_fsm_wait_lock_check, lock_r,
         pcs_reset_done_i, wait_pcs_done_i,
pcs_error_r1,wait_ready_done_i,
         pcs_error_count_done_i,init_state_r)
  variable init_fsm_name : string(1 to 25);
begin
  case init_state_r is

    when C_RESET =>

      init_next_state_r <= C_PMA_RESET;
      init_fsm_name := ExtendString("C_RESET", 25);

    when C_PMA_RESET =>

      if (pma_reset_done_i = '1') then
        init_next_state_r <= C_WAIT_LOCK;
      else
        init_next_state_r <= C_PMA_RESET;
      end if;
      init_fsm_name := ExtendString("C_PMA_RESET", 25);

    when C_WAIT_LOCK =>

      if(init_fsm_wait_lock_check = '1') then
        init_next_state_r <= C_PCS_RESET;
      else
        init_next_state_r <= C_WAIT_LOCK;
      end if;
      init_fsm_name := ExtendString("C_WAIT_LOCK", 25);

    -- some cases removed

    when others =>
      init_next_state_r <= C_RESET;
      init_fsm_name := ExtendString("C_RESET", 25);

    end case;
end process;

 

[Mike Treseler]

I am working with Xilinx tools and have troubles understanding the
purpose of a string variable init_fsm_name in the FSM process posted below
The code below was generated by Xilinx Core Generator.
I guess it must be related to simulation, but simulation tools can
already extract the name from the FSM state init_state_r.
I would be grateful for shedding a light regarding this question.

If I write my own synthesis code, I can use the same vhdl or verilog
code directly for synthesis or as a simulation model. If I use a vendor
core, no such vhdl source is provided. Vendor core generators collect
parameter strings from me to generate a vendor-specific netlist for
synthesis and a vhdl (or verilog) simulation model based on my entered
parameters.
Note that my synthesis input is a collection of strings, not code.

Your code example is probably part of such a simulation model.
I don't spend any time analyzing such code because:
1. It is not safe to touch it because I don't have the core source, and
2. If provides little useful information on how equivalent synthesis
code might be written.

If I were a fpga vendor, I might want my generated models to
work well enough to test the core without revealing the design
to the user.

-- Mike Treseler

 

[a s]

If I write my own synthesis code, I can use the same vhdl or verilog
code directly for synthesis or as a simulation model. If I use a vendor
core, no such vhdl source is provided. Vendor core generators collect
parameter strings from me to generate a vendor-specific netlist for
synthesis and a vhdl (or verilog) simulation model based on my entered
parameters.
Note that my synthesis input is a collection of strings, not code.

Your code example is probably part of such a simulation model.
I don't spend any time analyzing such code because:
1. It is not safe to touch it because I don't have the core source, and
2. If provides little useful information on how equivalent synthesis
code might be written.

If I were a fpga vendor, I might want my generated models to
work well enough to test the core without revealing the design
to the user.

Mike, thanks for the input. I completely agree that one should not
modify the code generated with a "wizard". I am just trying to
understand the purpose of that code as I am still learning VHDL.

BTW, the code sample is taken from the code which is responsible
for initialization of RocketIO in Virtex4, but I have seen similar
constructs in other Xilinx "wizard" generated code.