Question on Comparing two std logic vecter

[Tha]

Hi, I am new on VHDL, and I am writing a code that comparing two 32 bits std_logic_vector. If they are equal, a result of all one bits is produce, otherwise, a result of all zero bits is produce.
However, when I simulate my code, the following warnings appears:
WARNING: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
and I didn't get the correct result. My tb values are:
a = 00000000000001111111111111111111
b = 00000000000001111111111111111111
the result should be 32 1's
but it gave me 32 0's.
Can anyone please help me out? Thank you so much!

The following is my code:
entity ceq is
port(ra : in std_logic_vector(31 downto 0);
rb : in std_logic_vector(31 downto 0);
rt : out std_logic_vector(31 downto 0));
end ceq;

architecture ceq_stru of ceq is
signal rts : std_logic_vector(31 downto 0);
begin
comp: process (ra, rb)
variable count : std_logic_vector (31 downto 0)
:= "00000000000000000000000000000000";
begin
rts <= ra xor rb;
if rts = count then
rt <= (others => '1');
else
rt <= count;
end if;

end process comp;

end ceq_stru;

 

[Tha]

Okay, just after I post this thread , I found out why my code doesn't work.

"Note that this library doesn't allow you to do comparisons on std_logic_vector values. That's because it's impossible for it to determine whether a particular std_logic_vector is representing a signed or unsigned value. To do this, you need to use either the std_logic_unsigned or std_logic_signed libraries."

referred from http://www.cs.sfu.ca/~ggbaker/reference/std_logic/arith/comp.html

 

[joris]

The problem is signal semantics - signals are updated only after "one delta" - that is, at the end of the process.

It should work correctly after making rts a variable.

 

[eliascm]

XOR

You should be using XNOR. XOR is 0 when the bits are alike, while XNOR is 1.

 

[eliascm]

XOR Correction

Sorry, I goofed, you are looking for zeros.