Range of records

[hssig]

Hi,

I have the following declaration:


type A is record
first : std_logic;
second : std_logic;
third : std_logic;
end record A;

type B is record
one : std_logic;
two : A;
end record B;

signal sig : B;

Now I want to check if all A record elements of signal sig are zero:

process
begin
.....
if sig.two = (sig.two'range => '0') then
-- error message:Attribute "range" prefix must be appropriate for
an array (object or type mark).
end if;
end process;

Is there some possibility to check the record elements ?

cheers,
hssig

 

[Chris Higgs]

On 4/29/2010 8:09 AM, hssig wrote:
Nothing built-in that I know of that's not a syntactic train wreck.  But
this is VHDL; functions are your friend.  You know what your data types
look like, just write one that goes through each data element doing your
comparison and returns a boolean.

I define a to_vector and from_vector function for every record and pop
it in a package called "conversions". Then you can do something like
this:

library mylib;
use mylib.conversions.all;
....

if or_reduce(to_vector(sig.two)) = '0' then


Also putting records through fifos etc is nice and easy:

wrdata <= to_vector(my_record_type);
rdata <= from_vector(rdata_vec);

For extra points auto-generate the conversions package

Thanks,

Chris

 

[hssig]

Thank your for your proposals.

Cheers,
hssig

 

[Paul Uiterlinden]

Hi,

I have the following declaration:


type A is record
first : std_logic;
second : std_logic;
third : std_logic;
end record A;

type B is record
one : std_logic;
two : A;
end record B;

signal sig : B;

Now I want to check if all A record elements of signal sig are zero:

process
begin
....
if sig.two = (sig.two'range => '0') then
-- error message:Attribute "range" prefix must be appropriate for
an array (object or type mark).
end if;
end process;

Is there some possibility to check the record elements ?

Instead of "sig.two'range" use "others". You can use "others" only if the
record elements are of equal type.

This compiles cleanly:

ENTITY ent IS
END ENTITY ent;

LIBRARY ieee;
USE ieee.std_logic_1164.ALL;

ARCHITECTURE arch OF ent IS
TYPE a IS
RECORD
first : std_logic;
second : std_logic;
third : std_logic;
END RECORD a;

TYPE b IS
RECORD
one : std_logic;
two : a;
END RECORD b;

SIGNAL sig : b;
BEGIN

PROCESS (sig.two) IS
BEGIN
IF sig.two = (OTHERS => '0') THEN
REPORT "Zarro";
END IF;
END PROCESS;

END ARCHITECTURE arch;