[that he wanted to convert between this structure...]
type e_DdrCmdType is (WrRq, RdRq);
type t_DdrCmd is record
CmdType : e_DdrCmdType;
RowNr : std_logic_vector(3 downto 0);
ColNr : std_logic_vector(10 downto 0);
BnkNr : std_logic;
end record;
[...and a 17-bit std_logic_vector.]
Just a few conversion functions, that's all.
The following could be coded more concisely using
aggregates and concatenations, but I rather like
the ability to use named subtypes and constants
to parameterise which bit goes where. (You haven't
told us that, so it needs to be flexible!!!)
Might be a good idea to put all this stuff in the
same package that defines the types, so it's all
gathered together in one place.
This is definitely OK with ModelSim; I haven't
checked whether XST is clever enough to synthesise it.
It shouldn't be a problem, but you never know...
----------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use <whatever pkg defines your types>.all;
package DdrTypeMapper is
-- Subtype to reflect the FIFO i/o ports:
subtype slv_DdrCmd is std_logic_vector(16 downto 0);
-- Integer subtypes and constants that allow you to
-- parameterise which bits live where.
-- Constants for scalars, ranges for vectors.
constant slv_CmdType : natural := 16;
subtype slv_RowNr is natural range 15 downto 12;
subtype slv_ColNr is natural range 11 downto 1;
constant slv_BnkNr : natural := 0;
-- Convert between e_DdrCmdType and std_ulogic:
function to_sl(CmdType: e_DdrCmdType) return std_ulogic;
function to_e_DdrCmd(s: std_ulogic) return e_DdrCmdType;
-- Convert between slv_DdrCmd and t_DdrCmd:
function to_slv(cmd: t_DdrCmd) return slv_DdrCmd;
function to_t_DdrCmd(s: slv_DdrCmd) return t_DdrCmd;
end package DdrTypeMapper;
package body DdrTypeMapper is
-- Convert between e_DdrCmdType and std_ulogic:
function to_sl(CmdType: e_DdrCmdType) return std_ulogic is
begin
case CmdType is
when WrRq => return '0';
when RdRq => return '1';
end case;
end;
--
function to_e_DdrCmd(s: std_ulogic) return e_DdrCmdType is
begin
case s is
when '0'|'L' => return WrRq;
when '1'|'H' => return RdRq;
when others =>
report "metavalue in to_e_DdrCmd, returning WrRq"
severity WARNING;
return WrRq;
end case;
end;
-- Convert between slv_DdrCmd and t_DdrCmd:
function to_slv(cmd: t_DdrCmd) return slv_DdrCmd is
variable result: slv_DdrCmd;
begin
result(slv_CmdType) := to_sl(cmd.CmdType);
result(slv_RowNr) := cmd.RowNr;
result(slv_ColNr) := cmd.ColNr;
result(slv_BnkNr) := cmd.BnkNr;
return result;
end;
function to_t_DdrCmd(s: slv_DdrCmd) return t_DdrCmd is
variable result: t_DdrCmd;
begin
result.CmdType := to_e_DdrCmd(s(slv_CmdType));
result.RowNr := s(slv_RowNr);
result.ColNr := s(slv_ColNr);
result.BnkNr := s(slv_BnkNr);
return result;
end;
end package body DdrTypeMapper;
-----------------------------------------------------------
Hope this helps.
--
Jonathan Bromley, Consultant
DOULOS - Developing Design Know-how
VHDL * Verilog * SystemC * Perl * Tcl/Tk * Verification * Project Services
Doulos Ltd. Church Hatch, 22 Market Place, Ringwood, Hampshire, BH24 1AW, UK
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