T
THurkmans
Hello,
I've made a design in which I have a few blocks which I want to
synthesize. My simulation is working, and now I'm trying to do a post-
synthesis simulation per block by replacing each block with its
synthesized version.
What I didn't expect from my synthesis tool was that it would mess up
my entities in which I use records. I have created a small records to
pass my memories to my block:
type ram_image_type is record
enable : std_logic;
write_enable : std_logic;
address : std_logic_vector(17 downto 0);
inoutput : std_logic_vector(7 downto 0);
end record;
type memories_inout_type is record
image0 : ram_image_type;
image1 : ram_image_type;
image2 : ram_image_type;
end record;
I've found posts which create to_vec and from_vec, and align the
vectors such that they can be used in one std_logic_vector, but those
only assume one record. How can I create a to_std_logic_vector for the
memories_inout_type record?
I've made a design in which I have a few blocks which I want to
synthesize. My simulation is working, and now I'm trying to do a post-
synthesis simulation per block by replacing each block with its
synthesized version.
What I didn't expect from my synthesis tool was that it would mess up
my entities in which I use records. I have created a small records to
pass my memories to my block:
type ram_image_type is record
enable : std_logic;
write_enable : std_logic;
address : std_logic_vector(17 downto 0);
inoutput : std_logic_vector(7 downto 0);
end record;
type memories_inout_type is record
image0 : ram_image_type;
image1 : ram_image_type;
image2 : ram_image_type;
end record;
I've found posts which create to_vec and from_vec, and align the
vectors such that they can be used in one std_logic_vector, but those
only assume one record. How can I create a to_std_logic_vector for the
memories_inout_type record?