Recurse wait not supported or bad place of Exit or Next statement (Error msg)

[--MMS--]

What could mean the next error message?

" ERROR:Xst:844 - Recurse wait not supported or bad place of Exit or
Next statement. "

Next is the code. I took it from an example of a system/model named
Parwan (PAR-1):

--cache---
---

LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
USE work.types.ALL;
USE work.synthesis_parameters.ALL;
USE work.synthesis_utilities.ALL;


ENTITY cache IS
PORT (clk : IN std_logic;
-- cpu signals
read_mem, write_mem : INOUT std_logic;
halted, ready : OUT std_logic;
databus : INOUT byte := "ZZZZZZZZ";
adbus : INOUT veinte := "ZZZZZZZZZZZZZZZZZZZZ"
);
END cache;
--
ARCHITECTURE control_and_memory OF cache IS
SUBTYPE ways IS INTEGER RANGE 0 TO 1;
SUBTYPE sets IS INTEGER RANGE 0 TO 31;
TYPE line IS ARRAY (0 TO 0) OF byte;
SUBTYPE tags IS std_logic_vector (6 DOWNTO 0);
TYPE lru_type IS ARRAY (sets) OF ways;
TYPE entry IS RECORD
valid : BOOLEAN;
tag : tags;
data : line;
END RECORD;
TYPE each_cache IS ARRAY (sets) OF entry;
TYPE cache_type IS ARRAY (ways) OF each_cache;
SIGNAL cache : cache_type;
SIGNAL lru : lru_type;

BEGIN
PROCESS
VARIABLE s : sets;
VARIABLE hit : BOOLEAN; VARIABLE w, free : ways;
TYPE ww IS ARRAY(ways) OF ways;
CONSTANT nw : ww := (1, 0);
ALIAS set_value : std_logic_vector (4 DOWNTO 0) IS adbus (4 DOWNTO
0);
ALIAS tag_value : tags IS adbus (11 DOWNTO 5);
BEGIN
halted <= '0';
ready <= '0';

WAIT UNTIL clk = '0';
s := bits_to_int(To_bitvector(set_value));
hit := FALSE;
FOR i IN ways LOOP
IF cache(i)(s).tag = tag_value AND cache(i)(s).valid THEN
hit := TRUE; w := i;
END IF;
END LOOP;
IF hit THEN
ready <= '1';
lru (s) <= nw (w);
IF read_mem = '1' THEN
databus <= cache(w)(s).data(0);
WAIT UNTIL read_mem = '0';
databus <= "ZZZZZZZZ";
ELSIF write_mem = '1' THEN
cache(w)(s).data(0) <= databus;
cache(w)(s).valid <= TRUE;
write_mem <= '1';
--WAIT UNTIL grant_mem = '1';
--mem_databus <= databus; mem_adbus <= adbus;
WAIT UNTIL read_mem = '1';
databus <= "ZZZZZZZZ";
adbus <= "ZZZZZZZZZZZZZZZZZZZZ";
write_mem <= '0';
ready <= '1';
WAIT UNTIL write_mem = '0';
END IF;
ready <= '0';
ELSE
free := lru (s);
lru (s) <= nw (lru (s));


IF write_mem = '1' THEN
cache(free)(s).tag <= tag_value;
cache(free)(s).data(0) <= databus;
cache(free)(s).valid <= TRUE;
write_mem <= '1';
--WAIT UNTIL grant_mem = '1';
--mem_databus <= databus; mem_adbus <= adbus;
--WAIT UNTIL ready_mem = '1';
databus <= "ZZZZZZZZ";
adbus <= "ZZZZZZZZZZZZZZZZZZZZ";
write_mem <= '0';
ready <= '1';

WAIT UNTIL write_mem = '0';
ready <= '0';


ELSIF read_mem = '1' THEN
read_mem <= '1';
--WAIT UNTIL grant_mem = '1';
--mem_adbus <= adbus;
--WAIT UNTIL ready_mem = '1';
cache(free)(s).tag <= tag_value;
cache(free)(s).data(0) <= databus;
cache(free)(s).valid <= TRUE;
databus <= databus;
adbus <= "ZZZZZZZZZZZZZZZZZZZZ";
read_mem <= '0';
ready <= '1';
WAIT UNTIL read_mem = '0';
ready <= '0';
END IF;
END IF;
WAIT UNTIL (read_mem OR write_mem) = '1';
END PROCESS;
END control_and_memory;

-------------------

The error is referring to the code line " BEGIN PROCESS" after
"SIGNAL lru : lru_type;"


Thank you in advance,
MMS

 

[Ben Jones]

What could mean the next error message?

" ERROR:Xst:844 - Recurse wait not supported or bad place of Exit or
Next statement. "

Next is the code. I took it from an example of a system/model named
Parwan (PAR-1):

<snip>

That code is not synthesizable (by current commercially available
technologies at least), because it contains multiple wait statements. The
error message is a roundabout way of telling you that.

Cheers,

-Ben-

 

[Andy]

What could mean the next error message?



<snip>

That code is not synthesizable (by current commercially available
technologies at least), because it contains multiple wait statements. The
error message is a roundabout way of telling you that.

Cheers,

-Ben-

There are cases where "multiple" wait statements are allowed, as in a
wait statement inside a loop for some synthesis tools.

Regardless of that, the other problem here is that the OP is initially
waiting on a clock (implying a synchronous circuit), but then waits
for an asynchronous event (wait until read_mem = '0'). Not good.
Think about the hardware that would be required to implement such a
behavior...

Andy