E
Edward Watts
Hi all,
I posted a short while ago about using generate statements to select
out sections of a parallel signal or to combine sections into a
parallel signal (serial-ish to parallel and parallel to serial-ish
converters)
http://groups.google.com/group/comp.lang.vhdl/browse_thread/thread/67501029fa8041c6
The input serial to parallel works fine, and is synthesised and
general.
The output parallel to serial syntactically is fine, but won't
synthesis:
I'm using Xilinx 7.1i Foundation, and the code is the following
output_g : for i in 0 to NumberOfOutputOperands-1
generate
outputSlice_g : for j in 0 to NumberOfOutputBitGroups-1
generate
outputSliceLast_g : if (j = NumberOfOutputBitGroups-1) and (i =
NumberOutputOperands-1)
generate
process(clk)
if rising_edge(clk) then
if RSTIn = '1' then
...reset code.
else
result_internal <= result(i)( (j+1)*OutputWidth - 1 downto
j*OutputWidth );
-- other IO stuff.
end if;
end if;
end process;
end generate;
-- similar generate for all other output slices.
end generate;
end generate;
And the problem with this code is that a synthesis error occurs:
multi-source in Unit ... on signal result_internal<...>
VHDL requires that the process statement be inside the generate
statement, and not the other way around. Is there an option to use
perhaps a block statement to replicate the behaviour.
I've now tried to create a mux tree structure with a function, which
crashed the synthesis tool.
Here's the function, based off a reduction operator:
There were two errors raised, one at line 0 of this file of "Overflow
in constant operation", and the other is pointed out in the source
code.
function mux_build ( arg: std_logic_vector, a : std_logic_vector )
return std_logic_vector is
variable Result, Upper, Lower : std_logic_vector( SizeOfOutputBus-1
downto 0 );
variable Half : integer;
variable internal : std_logic_vector( arg'length-1 downto 0 );
begin
internal := arg;
if ( internal'length = SizeOfOutputBus ) then
Result := internal;
else
Half := 2**(internal'length-1);
Upper := mux_build( internal( internal'left downto Half ), a );
--gives "Use of null array slice on signal <internal> is not supported"
Lower := mux_build( internal( Half-1 downto internal'right), a );
if ( a( internal'length-SizeOfOutputBus-1) = '1' ) then
Result := Upper;
else
Result := Lower;
end if;
end if;
return Result;
end function;
Can someone help me with the nitty gritty of the language? I haven't
had too much experience with functions and synthesis.
Thanks,
ed.
I posted a short while ago about using generate statements to select
out sections of a parallel signal or to combine sections into a
parallel signal (serial-ish to parallel and parallel to serial-ish
converters)
http://groups.google.com/group/comp.lang.vhdl/browse_thread/thread/67501029fa8041c6
The input serial to parallel works fine, and is synthesised and
general.
The output parallel to serial syntactically is fine, but won't
synthesis:
I'm using Xilinx 7.1i Foundation, and the code is the following
output_g : for i in 0 to NumberOfOutputOperands-1
generate
outputSlice_g : for j in 0 to NumberOfOutputBitGroups-1
generate
outputSliceLast_g : if (j = NumberOfOutputBitGroups-1) and (i =
NumberOutputOperands-1)
generate
process(clk)
if rising_edge(clk) then
if RSTIn = '1' then
...reset code.
else
result_internal <= result(i)( (j+1)*OutputWidth - 1 downto
j*OutputWidth );
-- other IO stuff.
end if;
end if;
end process;
end generate;
-- similar generate for all other output slices.
end generate;
end generate;
And the problem with this code is that a synthesis error occurs:
multi-source in Unit ... on signal result_internal<...>
VHDL requires that the process statement be inside the generate
statement, and not the other way around. Is there an option to use
perhaps a block statement to replicate the behaviour.
I've now tried to create a mux tree structure with a function, which
crashed the synthesis tool.
Here's the function, based off a reduction operator:
There were two errors raised, one at line 0 of this file of "Overflow
in constant operation", and the other is pointed out in the source
code.
function mux_build ( arg: std_logic_vector, a : std_logic_vector )
return std_logic_vector is
variable Result, Upper, Lower : std_logic_vector( SizeOfOutputBus-1
downto 0 );
variable Half : integer;
variable internal : std_logic_vector( arg'length-1 downto 0 );
begin
internal := arg;
if ( internal'length = SizeOfOutputBus ) then
Result := internal;
else
Half := 2**(internal'length-1);
Upper := mux_build( internal( internal'left downto Half ), a );
--gives "Use of null array slice on signal <internal> is not supported"
Lower := mux_build( internal( Half-1 downto internal'right), a );
if ( a( internal'length-SizeOfOutputBus-1) = '1' ) then
Result := Upper;
else
Result := Lower;
end if;
end if;
return Result;
end function;
Can someone help me with the nitty gritty of the language? I haven't
had too much experience with functions and synthesis.
Thanks,
ed.