Hello,
I am thinking about defining a new HDL language, that will be more modern than VHDL (and Verilog) and allow a little higher level behavioral description than VHDL. For this language, I am beeing influenced by VHDL, Ada, Ruby and MyHDL. In short, it will be like an enhanced VHDL language that aims to be especially attractive for VHDL developpers. I also would like to write its compiler in Ada.
I don't know if it is a project that I will abandon as fast as it popped up in my mind, or not
.
Anyways, I made a document with my first reflexions for this new language. I currently don't have the right to post links because I need a few more posting. So to have the link, remove the spaces of :
http :// hdl-eesi.rhcloud . com
I think it's a good idea to ask for feedback before I go too far, so what are your feedbacks ?
Cheers,
Jonas
I am thinking about defining a new HDL language, that will be more modern than VHDL (and Verilog) and allow a little higher level behavioral description than VHDL. For this language, I am beeing influenced by VHDL, Ada, Ruby and MyHDL. In short, it will be like an enhanced VHDL language that aims to be especially attractive for VHDL developpers. I also would like to write its compiler in Ada.
I don't know if it is a project that I will abandon as fast as it popped up in my mind, or not
.Anyways, I made a document with my first reflexions for this new language. I currently don't have the right to post links because I need a few more posting. So to have the link, remove the spaces of :
http :// hdl-eesi.rhcloud . com
I think it's a good idea to ask for feedback before I go too far
, so what are your feedbacks ?Cheers,
Jonas