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- Aug 3, 2007
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Hi,
pls help me out from this thing is that i generate BRam using coregen with .cof file also and when i try to simulate the Design in model sim then error is coming like fail to open vhdl file ram_block.mif in rb mode.
I am in big trouble,pls reply...
Dinesh
IIT,Delhi
pls help me out from this thing is that i generate BRam using coregen with .cof file also and when i try to simulate the Design in model sim then error is coming like fail to open vhdl file ram_block.mif in rb mode.
I am in big trouble,pls reply...
Dinesh
IIT,Delhi