T
timinganalyzer
Hi All,
A newly added feature of the TimingAnalyzer is the ability to
read .vcd files. These files can be generated by logic simulators or
tools like Xilinx chipscope, or test equipment like logic analyzers.
So, you can easily make annotated timing diagrams from simulation or
test equipment outputs.
Would it be possible to email any .vcd files samples that you might
have, that are not proprietary, so I can test this feature with .vcd
files from as many sources as possible?
(e-mail address removed)
(e-mail address removed)
Thank you in advance,
Dan
www.timing-diagrams.com
A newly added feature of the TimingAnalyzer is the ability to
read .vcd files. These files can be generated by logic simulators or
tools like Xilinx chipscope, or test equipment like logic analyzers.
So, you can easily make annotated timing diagrams from simulation or
test equipment outputs.
Would it be possible to email any .vcd files samples that you might
have, that are not proprietary, so I can test this feature with .vcd
files from as many sources as possible?
(e-mail address removed)
(e-mail address removed)
Thank you in advance,
Dan
www.timing-diagrams.com