Richiesta aiuto per analisi codice VHDL

[flatiron]

Dear all,
I'm learning VHDL, after some simple example I've go to closely look
at the implementation of this "one shot delay generator", here below
the full code:

****CODE START****
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

-- entity definition

entity pulse_5clk is
port(
clk, reset: in std_logic;
go, stop: in std_logic;
pulse: out std_logic
);
end pulse_5clk;

-- architecture definition

architecture fsmd_arch of pulse_5clk is
constant P_WIDTH: natural := 5;
type fsmd_state_type is (idle, delay);
signal state_reg, state_next: fsmd_state_type;
signal c_reg, c_next: unsigned(3 downto 0);
begin
-- state and data registers
process(clk, reset)
begin
if (reset = '1') then
state_reg <= idle;
c_reg <= (others => '0');
elsif (clk'event and clk='1') then
state_reg <= state_next;
c_reg <= c_next;
end if;
end process;
-- next state logic & data path functional units/routing
process(state_reg,go,stop,c_reg)
begin
pulse <= '0';
c_next <= c_reg;
case state_reg is
when idle =>
if go='1' then
state_next <= delay;
else
state_next <= idle;
end if;
c_next <= (others => '0');
when delay =>
if stop='1' then
state_next <= idle;
else
if (c_reg = P_WIDTH - 1) then
state_next <= idle;
else
state_next <= delay;
c_next <= c_reg + 1;
end if;
end if;
pulse <= '1';
end case;
end process;
end fsmd_arch;
****CODE END****

I've take the simulation by using Modelsim and all is working
correctly but I've a question about the last process. Into the last
process (the state logic & data path) I've this statement (just after
the begin statement):

pulse <= '0';

then, if I'm not worong, the output signal with name pulse should be
set immediatly to 0, but into the simulation this never occour and the
behaviour of the output signal look right (pulse signal goes to 0 only
after the counter has elapsed).
Someone can gimme some explanation about this type of behaviour? Why
the statement pulse <= '0' is don't able to force immediatly to 0 the
pulse signal when the execution of the last process take to begin?.

Thanks in advance for every advice.
Powermos

 

[Mike Treseler]

Someone can gimme some explanation about this type of behaviour? Why
the statement pulse <= '0' is don't able to force immediatly to 0 the
pulse signal when the execution of the last process take to begin?.

Because signal assignments are not activated immediately.
The last assignment traced before the end of the process wins.

I find this annoying also, and switched to variables
in a single clocked process to avoid it. Examples here:
http://mysite.verizon.net/miketreseler/

-- Mike Treseler

 

[flatiron]

Because signal assignments are not activated immediately.
The last assignment traced before the end of the process wins.

I find this annoying also, and switched to variables
in a single clocked process to avoid it. Examples here:http://mysite.verizon.net/miketreseler/

  -- Mike Treseler

Dear Mike,
thanks you very much for the explanation, now I can see the ligth to
go out the tunnel

Bye
Powermos