ROM

[u_stadler]

hi

i have a problem:

i created a lookup Table:

type SBOX_TYPE is array ( 0 to 255) of std_logic_vector(7 downto 0);

constant SBOX_Table: SBOX_TYPE := ( ........ );

in my actual code i have a state machine with different states. i have
4 states (sub0 to sub3) in which i call SBOX_TABLE.these states can
never be acticve at the same time.

if s_State_Sub0 = '1' then
v_Word(0) <= SBOX_Table(conv_integer(v_Word(0)));
s_Next_State_Sub0 <= '0';
s_Next_State_Sub1 <= '1';
end if;
if s_State_Sub1 = '1' then
v_Word(1) <= SBOX_Table(conv_integer(v_Word(1)));
s_Next_State_Sub1 <= '0';
s_Next_State_Sub2 <= '1';
end if;
if s_State_Sub2 = '1' then
v_Word(2) <= SBOX_Table(conv_integer(v_Word(2)));
s_Next_State_Sub2 <= '0';
s_Next_State_Sub3 <= '1';
end if;
if s_State_Sub3 = '1' then
v_Word(3) <= SBOX_Table(conv_integer(v_Word(3)));
s_Next_State_Sub3 <= '0';
s_Next_State_RCON <= '1';
end if;

when i synthesize my code now (im using the xilinx web pack ise 7.3) it
generates 4 rom tables which use a lot of space. how can i reduce this
to one since i never access it at the same time?

another question: do things like type conversions (for example
conv_integer) get synthesized or is it just for the simulation? i don't
think so because its all a bit vector in hardware anyway.

thanks

 

[Ralf Hildebrandt]

if s_State_Sub0 = '1' then
v_Word(0) <= SBOX_Table(conv_integer(v_Word(0)));
s_Next_State_Sub0 <= '0';
s_Next_State_Sub1 <= '1';
end if;
if s_State_Sub1 = '1' then
v_Word(1) <= SBOX_Table(conv_integer(v_Word(1)));
s_Next_State_Sub1 <= '0';
s_Next_State_Sub2 <= '1';
end if; ....
when i synthesize my code now (im using the xilinx web pack ise 7.3) it
generates 4 rom tables which use a lot of space. how can i reduce this
to one since i never access it at the same time?

If so you may use

if () then
elsif () then
else
end if;

Don't forget the last else to save logic (use it for the last option).

another question: do things like type conversions (for example
conv_integer) get synthesized or is it just for the simulation? i don't
think so because its all a bit vector in hardware anyway.

You are right.


Ralf

 

[u_stadler]

hi ralf!

thanks for the answer!
i tried ti use if/elsif insted but it still creates 4 roms?!
any ideas?

thanks
urban

 

[Mike Treseler]

generates 4 rom tables which use a lot of space. how can i reduce this
to one since i never access it at the same time?

You can't if you need access to all four.

another question: do things like type conversions (for example
conv_integer) get synthesized or is it just for the simulation? i don't
think so because its all a bit vector in hardware anyway.

A type conversion corresponds
to getting the wires hooked up right.


-- Mike Treseler

 

[u_stadler]

well i do need access to all four but not at the same time.
i want to substitute one byte after the other to save space. i don't
need four equal sboxe's in my design. isn't there a way to achive this?

 

[mk]

well i do need access to all four but not at the same time.
i want to substitute one byte after the other to save space. i don't
need four equal sboxe's in my design. isn't there a way to achive this?

define SBOX as a separate entity with an address input port and a data
output port. then in your state machine, assign values to the address
variable. this way your tool will be able to generate a mux for the
address and you'll need only one copy of the SBOX.