ror and sla in vhdl

[sri4ever]

Hi,
I am a beginner in VHDL. I am trying to test ror and sla in vhdl with the following code using Xlinix 12.1 .
library IEEE;
use IEEE.NUMERIC_STD.ALL;



entity shiftoperators is
port ( A : in bit_vector ( 2 downto 0) := "101" ;
B : in bit_vector ( 2 downto 0) := "011";
C : in bit_vector ( 2 downto 0) := "010"
);

end shiftoperators;

architecture Behavioral of shiftoperators is

begin

(A&B) or (B & C); ----- line 44
(A ror 2); ---- line 45
(A sla 2); ---- line 46
A & not B; --- line 47
A or B and C; --- line 48



end Behavioral;

but i get the following errors:
Line 44. parse error, unexpected OR, expecting LE
Line 45. parse error, unexpected SEMICOLON, expecting LE
Line 46. parse error, unexpected SEMICOLON, expecting LE

kindly suggest where am i going wrong.


Thanks

 

[sri4ever]

Never mind, I was able to resolve the issue.
I replaced the number of bits to 6 for the concat part and that resolved it.