sens?

[Attila Csosz]

architecture behv of counter is

signal Pre_Q: unsigned( 3 downto 0 );

begin

-- behavior describe the counter

process(clock, clear)
begin
if clear = '1' then
Pre_Q <= "0000";
elsif (clock='1' and clock'event) then
Pre_Q <= Pre_Q + 1;
end if;
end process;

-- concurrent assignment statement
QA <= Pre_Q(3);
QB <= Pre_Q(2);
QC <= Pre_Q(1);
QD <= Pre_Q(0);

end behv;

 

[Mike Treseler]

architecture behv of counter is .. . .
end behv;

In this case: QB <= Pre_Q(2); sensitive to "Pre_Q" or only "Pre_Q(2)"?

In simulation, your process will rerun
every time Pre_Q changes.

Consider synching things up as below to speed
up your simulation.

-- Mike Treseler ---------------------

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity counter is

port (
clock : in std_ulogic;
clear : in std_ulogic;
QA : out std_ulogic;
QB : out std_ulogic;
QC : out std_ulogic;
QD : out std_ulogic
);
end entity counter;

architecture behv of counter is
begin
-- behavior describe the counter
process(clock, clear)
is
variable Pre_Q_v : unsigned(3 downto 0);
begin
if clear = '1' then
Pre_Q_v := "0000";
elsif (clock = '1' and clock'event) then
-- synchronous output assignments
QA <= Pre_Q_v(3);
QB <= Pre_Q_v(2);
QC <= Pre_Q_v(1);
QD <= Pre_Q_v(0);
-- inc counter
Pre_Q_v := Pre_Q_v + 1;
end if;
end process;
end behv;

 

[Attila Csosz]

. . .

Thanks, i will correct it. But anyway which? Because im working on an
vhdl compiler/interpreter.

Attila

 

[Mike Treseler]

Thanks, i will correct it. But anyway which? Because im working on an
vhdl compiler/interpreter.

The process

QB <= Pre_Q(2);

Is exactly the same as the process

process(Pre_Q)
begin
QB <= Pre_Q_v(2);
end process;

-- Mike Treseler

 

[Eyck Jentzsch]

The process

QB <= Pre_Q(2);

Is exactly the same as the process

process(Pre_Q)
begin
QB <= Pre_Q_v(2);
end process;

-- Mike Treseler

I think you are wrong, the process should be:

process(Pre_Q(2))
begin
QB <= Pre_Q(2);
end process;

because there is no such thing like an array signal in VHDL, it's always
an array of signals. But most modern compilers treat it in that way if
possible (e.g. no slices etc.) to gain a performance improvement.

-Eyck