E
ed
Hey Everyone,
I have some VHDL code, which has multiple inputs and outputs. I'm working
to a specification which specifies, among other things, a setup time and a
hold time. How can I find out the setup and hold times of the VHDL input
and outputs? The software I use is Xilinx ISE 4.2i.
Thanks in advance,
I have some VHDL code, which has multiple inputs and outputs. I'm working
to a specification which specifies, among other things, a setup time and a
hold time. How can I find out the setup and hold times of the VHDL input
and outputs? The software I use is Xilinx ISE 4.2i.
Thanks in advance,