shift register synthesis

[Markus]

Hello,

I need a little help in my VHDL design. I am currently trying to build
a memory test consisting of "walking 1" and "walking 0" pattern.
Simulation works fine and synthesis also passes timing requirements.
But in hardware only addressbus pattern passes.

The problem seems to be the 224 bit shift register for databus.

process (clk, reset)
if reset = '1' then
data <= (others => '0');
sreg <= (others => '0');
elsif clk = '1' and clk'EVENT then
if enable = '1' then
if load_sreg = '1' then
sreg (224 downto 1) <= (others => '0');
sreg (0) <= '1';
else
sreg <= sreg (223 downto 0) & '0';
end if;
end if;
data <= sreg;
end if;
end process;

This design passes Quartus with 0.018ns slack but in hardware this
pattern sometimes fails.

Do you have any ideas to create a "faster" shift register or to create
a "Walking 1" pattern in a more efficient way?

Thanks
Markus

 

[JK]

The problem seems to be the 224 bit shift register for databus.

Your code represents 225 bit shift regsiter, not 224 bit shift
register.

process (clk, reset)
if reset = '1' then
data <= (others => '0');
sreg <= (others => '0');
elsif clk = '1' and clk'EVENT then
if enable = '1' then
if load_sreg = '1' then
sreg (224 downto 1) <= (others => '0');
sreg (0) <= '1';
else
sreg <= sreg (223 downto 0) & '0';
end if;
end if;
data <= sreg;
end if;
end process;

You can keep signal data out of process.

This design passes Quartus with 0.018ns slack but in hardware this
pattern sometimes fails.

Your code dont check for 224 bit shifts. After 224 bit shifts, your
register will always be 0.
Fails means??? Can you put some light on this..

Regards,
JK