A
Abbes Amira
Short course: IMVIP 2004
http://www.cs.tcd.ie/IMVIP2004/ShortCourses.html
Accelerating Matrix Algorithms on Reconfigurable Hardware for Image
and Signal Processing Applications presented by Dr. Abbes Amira,
Queens University, Belfast. (Provisional Schedule: Tuesday, August
31st 11.30-13.30).
"Accelerating Matrix Algorithms on Reconfigurable Hardware for Image
and Signal Processing Applications"
In this Course, Dr. Amira will be presenting a number of solutions and
tools to address and perform a range of applications in image, video
and signal processing, 3D graphics and scientific applications. Dr.
Amira will focus on the design, implementation and acceleration of
matrix algorithms such as matrix operations, transforms and
decompositions for image and signal processing using Field
Programmable Gates Arrays FPGAs, different architectures, arithmetic
techniques, design methodologies and design entries (Handel C,
Schematic and VHDL). A range of matrix algorithms will be addressed
including: Discrete Orthogonal Transforms DOTs for image and signal
processing, Matrix Multiplication for array processing, Fast Fourier
Transform (FFT) for frequency image filtering, Discrete Wavelet
Transform (DWT) for Image and Video Compression, Singular Value
Decomposition (SVD) for image denoising. Optimisation solutions will
be also presented for reconfigurable hardware design using intelligent
techniques. The problem of processing large matrices will be also
addressed in this course.
Course instructor
Dr. Abbes Amira obtained an "Ingéniorat d'Etat" degree in Electronics
and a DEA degree in image and speech processing from the National
Polytechnic School of Algiers "ENP", a PhD degree in Computer Science
and a PGCHET degree from Queen's University, Belfast (UK). He is
currently a lecturer in Computer Science at Queen's University,
Belfast, teaching computer architecture and algorithms and data
structures. His research interests are in Design and Implementation of
Digital Image and Signal Processing algorithms, Custom Computing using
Field Programmable Gate Array (FPGAs), Hardware/Software Co- Design,
System on Chip, Image Processing based Wavelet Transforms, Telecom
Applications, Information Systems, Artificial Intelligence,
Optimisation Techniques and Information Retrieval. He has written
several papers in peer-reviwed conferences and premier journals and
chaired a number of sessions in prestigious conferences. He is a
regular reviewer for several IEEE, ACM, Elsevier Journals and
Conferences such as DSP, TIP, ISCAS, ICASSP and DAC. Dr. Amira is a
member of IEEE, ACM and SIGDA.
He has carried out successful work in the use of FPGAs for
implementing a range of matrix algorithms for signal and image
processing applications. He is author of over 80 refereed conference
and journal papers during his career to date. In October 2001 he was
awarded an EPSRC grant for a proposal entitled "Coprocessor based
Matrix Algorithms for Image and Signal Processing". This is a
three-year project (worth £112,445). A number of solutions have been
successfully implemented for processing large matrix multiplications,
transforms and decompositions for image and signal processing
applications.
The research carried out during Dr. Amira's PhD project was concerned
with an investigation into the design and implementation of a range of
matrix algorithms such as matrix multiplication and one-dimensional
transforms using a novel custom coprocessor system for MATrix
algorithms based on Reconfigurable Computing (RCMAT). New algorithms
for matrix multiplication, using both systolic and distributed
arithmetic design methodologies have been developed. The architectures
developed for matrix multiplication exploit different arithmetic
techniques such as bit parallel, bit serial and digit serial design
methods. In addition, novel architectures were developed to perform
matrix transforms using both systolic and distributed arithmetic
design methodologies. These architectures are scalable, modular and
require less area and time complexity with reduced latency in
comparison with existing structures. One of the most notable
achievements of this work was a parallel matrix multiplier developed,
outperforming the PAMBlox multiplier developed at Stanford University,
USA.
Dr. Amira has been invited several times to give talks to Universities
and companies in UK and US, including University of Oakland at
Michigan State, USA, University of Dundee, Scotland, UK and ANDOR
company in Belfast.
http://www.cs.tcd.ie/IMVIP2004/ShortCourses.html
Accelerating Matrix Algorithms on Reconfigurable Hardware for Image
and Signal Processing Applications presented by Dr. Abbes Amira,
Queens University, Belfast. (Provisional Schedule: Tuesday, August
31st 11.30-13.30).
"Accelerating Matrix Algorithms on Reconfigurable Hardware for Image
and Signal Processing Applications"
In this Course, Dr. Amira will be presenting a number of solutions and
tools to address and perform a range of applications in image, video
and signal processing, 3D graphics and scientific applications. Dr.
Amira will focus on the design, implementation and acceleration of
matrix algorithms such as matrix operations, transforms and
decompositions for image and signal processing using Field
Programmable Gates Arrays FPGAs, different architectures, arithmetic
techniques, design methodologies and design entries (Handel C,
Schematic and VHDL). A range of matrix algorithms will be addressed
including: Discrete Orthogonal Transforms DOTs for image and signal
processing, Matrix Multiplication for array processing, Fast Fourier
Transform (FFT) for frequency image filtering, Discrete Wavelet
Transform (DWT) for Image and Video Compression, Singular Value
Decomposition (SVD) for image denoising. Optimisation solutions will
be also presented for reconfigurable hardware design using intelligent
techniques. The problem of processing large matrices will be also
addressed in this course.
Course instructor
Dr. Abbes Amira obtained an "Ingéniorat d'Etat" degree in Electronics
and a DEA degree in image and speech processing from the National
Polytechnic School of Algiers "ENP", a PhD degree in Computer Science
and a PGCHET degree from Queen's University, Belfast (UK). He is
currently a lecturer in Computer Science at Queen's University,
Belfast, teaching computer architecture and algorithms and data
structures. His research interests are in Design and Implementation of
Digital Image and Signal Processing algorithms, Custom Computing using
Field Programmable Gate Array (FPGAs), Hardware/Software Co- Design,
System on Chip, Image Processing based Wavelet Transforms, Telecom
Applications, Information Systems, Artificial Intelligence,
Optimisation Techniques and Information Retrieval. He has written
several papers in peer-reviwed conferences and premier journals and
chaired a number of sessions in prestigious conferences. He is a
regular reviewer for several IEEE, ACM, Elsevier Journals and
Conferences such as DSP, TIP, ISCAS, ICASSP and DAC. Dr. Amira is a
member of IEEE, ACM and SIGDA.
He has carried out successful work in the use of FPGAs for
implementing a range of matrix algorithms for signal and image
processing applications. He is author of over 80 refereed conference
and journal papers during his career to date. In October 2001 he was
awarded an EPSRC grant for a proposal entitled "Coprocessor based
Matrix Algorithms for Image and Signal Processing". This is a
three-year project (worth £112,445). A number of solutions have been
successfully implemented for processing large matrix multiplications,
transforms and decompositions for image and signal processing
applications.
The research carried out during Dr. Amira's PhD project was concerned
with an investigation into the design and implementation of a range of
matrix algorithms such as matrix multiplication and one-dimensional
transforms using a novel custom coprocessor system for MATrix
algorithms based on Reconfigurable Computing (RCMAT). New algorithms
for matrix multiplication, using both systolic and distributed
arithmetic design methodologies have been developed. The architectures
developed for matrix multiplication exploit different arithmetic
techniques such as bit parallel, bit serial and digit serial design
methods. In addition, novel architectures were developed to perform
matrix transforms using both systolic and distributed arithmetic
design methodologies. These architectures are scalable, modular and
require less area and time complexity with reduced latency in
comparison with existing structures. One of the most notable
achievements of this work was a parallel matrix multiplier developed,
outperforming the PAMBlox multiplier developed at Stanford University,
USA.
Dr. Amira has been invited several times to give talks to Universities
and companies in UK and US, including University of Oakland at
Michigan State, USA, University of Dundee, Scotland, UK and ANDOR
company in Belfast.