sift-register

[see-me]

hi

i wrote a code for shift-register with G_DATA_WIDTH bits and with G_SHIFT_REGISTER_SIZE registers

this is the code:

library IEEE;
use IEEE.std_logic_1164.all;

entity shift_register is
  generic( G_DATA_WIDTH : integer := 8;
		   G_SHIFT_REGISTER_SIZE : integer :=4);
  port(clk, enable,reset : in std_logic;
       data_in : in std_logic_vector(G_DATA_WIDTH-1 downto 0);
       data_out : out std_logic_vector(G_DATA_WIDTH-1 downto 0));
end shift_register;

architecture arc_shift_register of shift_register is
  component registerN 
  generic(G_DATA_WIDTH : integer := 8);
  port(clk, load,reset : in std_logic;
       data_in : in std_logic_vector(G_DATA_WIDTH-1 downto 0);
       data_out : out std_logic_vector(G_DATA_WIDTH-1 downto 0));
end component;
  signal  clock1,load1,reset1:  std_logic;
  signal in1:  std_logic_vector(G_DATA_WIDTH*G_SHIFT_REGISTER_SIZE-1 downto 0);
  signal out1:  std_logic_vector(G_DATA_WIDTH*G_SHIFT_REGISTER_SIZE-1 downto 0);



  
  

begin
 
     
  REG_GEN: for i in G_SHIFT_REGISTER_SIZE downto 1 generate
    RE:registerN
    generic map(G_DATA_WIDTH => G_DATA_WIDTH)
    port map(clk => clock1,load => load1,reset => reset1,
      data_in => in1((G_DATA_WIDTH*i)-1 downto (G_DATA_WIDTH*(i-1))),
      data_out => out1((G_DATA_WIDTH*i)-1 downto (G_DATA_WIDTH*(i-1))));
  end generate;

  
  process(clk,reset)
  begin 
    if reset='0' then data_out <=(others =>'0');
    elsif clk'event and clk='1' then
      in1((G_DATA_WIDTH*G_SHIFT_REGISTER_SIZE)-1 downto G_DATA_WIDTH*(G_SHIFT_REGISTER_SIZE-1)) <= data_in;
      for p in G_SHIFT_REGISTER_SIZE-1 downto 1 loop
      in1((G_DATA_WIDTH*p)-1 downto G_DATA_WIDTH*(p-1)) <= out1(G_DATA_WIDTH*(p+1)-1 downto G_DATA_WIDTH*p);
      end loop;
      data_out <= out1(G_DATA_WIDTH*1-1 downto G_DATA_WIDTH*(1-1));
      end if;
      end process;
end arc_shift_register;

configuration cfg_shift_register of shift_register is
  for arc_shift_register
  end for;
end cfg_shift_register;

when i compile it it succeed however when i run a test_banch it does not work corectly..

i think i know where the problem origin from:

when i generated (with the for loop) it generate the registers

however i cant understand something i want to change the whold data in the data_in of register 2 what is the code to do it??
i tried data_in(2) however it does not work for me i think because that it mean to chenge the second bit in data_in and not the data_in (G_DATA_WIDTH-1 downto 0) of register 2..

can you explain it to me?

and if you can see any problem with my code please let me know

thank very much i really like this forum you are great!