signal AND with a constant of '1'

[fl]

Hi,

I use Matlab HDL Coder generated VHDL code in my project. I find there is a line in which a signal AND with a constant '1'. Does that make sense in that writing? I can ignore such writing to a signal setting without AND the constant?


Thanks,

..............
CONSTANT const_one : std_logic := '1'; -- boolean

SIGNAL phase_0 : std_logic; -- boolean
SIGNAL phase_temp : std_logic; -- boolean

begin
phase_temp <= phase_0 AND const_one;
....
end

 

[rickman]

Hi,

I use Matlab HDL Coder generated VHDL code in my project. I find there is a line in which a signal AND with a constant '1'. Does that make sense in that writing? I can ignore such writing to a signal setting without AND the constant?


Thanks,

..............
CONSTANT const_one : std_logic := '1'; -- boolean

SIGNAL phase_0 : std_logic; -- boolean
SIGNAL phase_temp : std_logic; -- boolean

begin
phase_temp<= phase_0 AND const_one;
....
end

Certainly this won't make a difference logically. So you have to ask
why they would do this. If this were to be translated into hardware, it
is possible it would use a LUT in an FPGA or a gate in an ASIC, but all
the tools I know of will optimize this out automatically unless you turn
off the optimizations.

I can't see it hurting anything.

Rick

 

[KJ]

Hi, I use Matlab HDL Coder generated VHDL code in my project.
I find there is a line in which a signal AND with a constant '1'.
Does that make sense in that writing?

Machine generated code often contains things that look odd to human readers.. If you want to know the reason they define the constant in this instancethen you should contact the folks at Matlab.

I can ignore such writing
to a signal setting without AND the constant?

What does you mean by 'ignore such writing'?
- Don't look at it, accept it 'as-is' and move on? If so, then the answer is 'yes'
- Get rid of the constant and it's usage by editing the machine generated code to 'clean up' something you don't like? If so, then the answer is 'no'.. At best, all you can hope to accomplish with any edits is to not break working code. At worst, you break that working code. So don't bother editing.

Kevin Jennings

 

[Tricky]

Hi,



I use Matlab HDL Coder generated VHDL code in my project. I find there isa line in which a signal AND with a constant '1'. Does that make sense in that writing? I can ignore such writing to a signal setting without AND theconstant?





Thanks,



.............

CONSTANT const_one : std_logic := '1'; -- boolean



SIGNAL phase_0 : std_logic; -- boolean

SIGNAL phase_temp : std_logic; -- boolean



begin

phase_temp <= phase_0 AND const_one;

...

end

I bet someone did that in the original matlab/simulink model. They may haveintended to have something other than 1 connected to the other input of the AND gate at some point. I get to see this style of coding all over the legacy AHDL/schematic designs here.