Hi all,
This topic on signed operation in VHDL puzzles me a lot. first of all, i tried the subtraction operation using unsigned data type, then with the signed data type. Both gives the same output in simulation. can anyone please explain me this?
This topic on signed operation in VHDL puzzles me a lot. first of all, i tried the subtraction operation using unsigned data type, then with the signed data type. Both gives the same output in simulation. can anyone please explain me this?