simple synthesis errors

[eeh]

I am just beginner of vhdl. I write a simple vhdl code segment below
and find errors after synthesis. Could anyone teach me why the errors
arise?

entity test is
Port
(
inp:in integer;
output integer
);
end test;

architecture Behavioral of test is
type temp_typ is array(16 downto 0) of integer;
signal temp:temp_typ;
signal index:integer:=0;
signal i:integer;
signal sum:integer:=0;
begin

temp(index)<=inp;
index<=(index+1)mod 16;
for i in 0 to 15 loop
sum<=sum+temp(index)*inp;
index<=(index+1)mod 16;
end loop;
end Behavioral;

ERROR:HDLParsers:164 - "C:/terry/prj/fpga/counter/echo_can.vhd" Line
51. parse error, unexpected FOR
ERROR:HDLParsers:834 - "C:/terry/prj/fpga/counter/echo_can.vhd" Line
53. Signal index has a multi source.
ERROR:HDLParsers:164 - "C:/terry/prj/fpga/counter/echo_can.vhd" Line
54. parse error, unexpected LOOP, expecting SEMICOLON

 

[Karthikeyan Subramaniyam]

hi
you are trying to design combo logic and you have used sequential
statements without any process block. Try this.

-------------
architecture Behavioral of test is
type temp_typ is array(16 downto 0) of integer;

begin
process (inp)
variable temp:temp_typ;
variable i:integer;
variable index,sum:integer:=0;
begin
temp(index):=inp;
index:=(index+1)mod 16;
for i in 0 to 15 loop
sum:=sum+temp(index)*inp;
index:=(index+1)mod 16;
end loop;
outp <= sum;
end process;
end Behavioral;
----------------------

First you go through any VHDL basic tutorial before start coding.

Rgds,
Karthik

--
Karthikeyan Subramaniyam,
Verification Engineer,
TooMuch Semiconductor Solutions Pvt. Ltd.
www.toomuchsemi.com
A Bangalore based startup specialising on services in EDA & Verification.

 

[Andy Peters]

I am just beginner of vhdl. I write a simple vhdl code segment below
and find errors after synthesis. Could anyone teach me why the errors
arise?

entity test is
Port
(
inp:in integer;
output integer
);
end test;

architecture Behavioral of test is
type temp_typ is array(16 downto 0) of integer;
signal temp:temp_typ;
signal index:integer:=0;
signal i:integer;
signal sum:integer:=0;
begin

temp(index)<=inp;
index<=(index+1)mod 16;
for i in 0 to 15 loop
sum<=sum+temp(index)*inp;
index<=(index+1)mod 16;
end loop;
end Behavioral;

ERROR:HDLParsers:164 - "C:/terry/prj/fpga/counter/echo_can.vhd" Line
51. parse error, unexpected FOR
ERROR:HDLParsers:834 - "C:/terry/prj/fpga/counter/echo_can.vhd" Line
53. Signal index has a multi source.
ERROR:HDLParsers:164 - "C:/terry/prj/fpga/counter/echo_can.vhd" Line
54. parse error, unexpected LOOP, expecting SEMICOLON

I suggest that you purchase a VHDL textbook. I like Ashenden's book.

-a

 

[eeh]

How about if I want to do concurrent statements inside process? For
example, if I want to run statements A and B concurrently inside the
process below:

process (clk,data)
begin
if (clk'event and clk='1') then
qLocal <= qLocal(254 downto 0) & data; --statement A
outp <= qlocal(conv_integer(unsigned(sel))); --statement B
end if;
end process;