Simulate VHDL core model with C program

[zhangyu917]

Hi,

I have a VHDL model of a CPU core, say ARM soft core. Now, I am trying
to run some C programs on this VHDL core model to see if this core
functions right. How can I do this VHDL-C co-simulation in Modelsim? Do
I have to create some RAM model to preload the program, then feed the
RAM to the core? Is there any other ways to do this kind of simulation?

Please help, Many thanks in advance!

Yu

 

[Paul Uiterlinden]

Hi,

I have a VHDL model of a CPU core, say ARM soft core. Now, I am
trying
to run some C programs on this VHDL core model to see if this core
functions right. How can I do this VHDL-C co-simulation in Modelsim?
Do I have to create some RAM model to preload the program, then feed
the RAM to the core? Is there any other ways to do this kind of
simulation?

One way would be using Seamless by Mentor Graphics:
http://www.mentor.com/products/fv/hwsw_coverification/seamless/index.cfm

 

[Hans]

Hi Yu,

Hi,

I have a VHDL model of a CPU core, say ARM soft core. Now, I am trying
to run some C programs on this VHDL core model to see if this core
functions right. How can I do this VHDL-C co-simulation in Modelsim? Do
I have to create some RAM model to preload the program, then feed the
RAM to the core?

Yes, you are correct, this is probably the simplest way. If you look at my
design (http://www.ht-lab.com/freecores/cpu8086/cpu86.html) and many others
on the web you will find a simular setup. I use some LPM memory from Altera
that can load a hex file during elaboration. Thus my development flow is

1) compile code
2) create hex file and write to work directory
3) issue a restart -f
4) run simulation, find bug
5) change code, goto 1

A nice feature of these LPM memories and Quartus is that you can do the same
on a prototype board, i.e. you can re-load the memories without reloading
your whole design,

Hans
www.ht-lab.com