simulating Xilinx cores

[FPGA]

I would like to simulate some modules in Verilog along with a FIFO
generated by ISE core. I would like to know if it is possible to
simuate teh Xilinx generated cores. If so, which tools do I need to
use for that? Is there a free Xilinx simulator I could use to sereve
the purpose? I was using Modelsim till date. I dont think Modelsim
would recognize the Xilinx cores.
Your comments would be appreciated.

 

[hilal]

you could always download Xilinx ISE 9.2i Webpack which is a free version (don't contain all the models of their FPGA cores).

Then you can use the XST simulator built in ISE 9.2i, which should recognize the cores if you have the following packages:

library UNISIM;
use UNISIM.VComponents.all;

EDIT--- sorry I don't know how you would include these packages in Verilog, this is VHDL code.