Simulation Error While writing to file

[Mohammed khader]

Hi Vhdl Folks,

For the Process 'Read_HexFile_L' while simulating I got the
follwing error for the first time

KERNEL: Error: E8060 : Stack Overflow
# Fatal error occurred during simulation.

When I simulated next time after re comilation I got the another
error as

# KERNEL: Error: E8017 : Unknown error in kernel process module.
# Fatal error occurred during simulation.

Later it worked well when I used an intermediate variable to pass
the std_Logic_vector to the WRITE function as follows...

std_result:=CONV_STD_LOGIC_VECTOR(integer_result,SINCOS_WORD_LENGTH);
WRITE(SinCos_Vhd,std_result);

According to me CONV_STD_LOGIC_VECTOR is a function and can be used
in any expression or as parameter .But it did'nt work..

Please Help me in understanding this.....




Read_HexFile_Lrocess
file SinCos_Str: Text open read_mode is Hex_File;
type Std_File_Type is file of Std_Logic_Vector;
file SinCos_Vhd: Std_File_Type open write_mode is StdVec_File;
variable Ptr: Line;
variable ch:Character;
variable found:boolean:=false;
variable integer_result:Integer;
variable std_result:std_logic_vector(SINCOS_WORD_LENGTH-1 downto 0);
variable line_read:Natural:=0;
begin
ReadLine_L: while(not ENDFILE(SinCos_Str))loop
READLINE(SinCos_Str,Ptr);
found:=false;
Check_Start_L:for i in Ptr'range loop
READ(Ptr,ch);
if(ch = '$')then
found:=true;
exit Check_Start_L;
end if;
end loop Check_Start_L ;
if(found=true)then
READHEX(Ptr,integer_result);
WRITE(SinCos_Vhd,CONV_STD_LOGIC_VECTOR(integer_result,SINCOS_WORD_LENGTH));
line_read:=line_read+1;
end if;


end loop ReadLIne_L;
wait; -- Wait forever...
end process Read_HexFile_L;


Regards,
Mohammed Khader.

 

[Neo]

Hi,
I think the problem is not with conversion function but with the write
function, it wont take arguments which are functions or some other
expressions other than whats to be written.


Neo.

 

[Mohammed khader]

Hi,
I think the problem is not with conversion function but with the write
function, it wont take arguments which are functions or some other
expressions other than whats to be written.


Neo.

I got this error during Simulation NOT while compling.

According to me first CONV_STD_LOGIC_VECTOR is executed then the
return value is passed to the WRITE function.

Please clarify me if I am wrong.

 

[Jim Lewis]

Mohammed,
Your post to the recent thread caused me to re-read this.

Submit this as a bug to your toool vendor. It
should have worked. You are using the VHDL built-in
write. It is implicitly defined. I cut the following
out of the LRM:

type FT is file of TM;
procedure WRITE (file F: FT; VALUE: in TM);


As long as the inputs to the functions and procedures
are constant class, you can call them using an expression.
If there is not class specified and the mode is in (as
marked above), then the class is constant. In fact, to
put you at ease with this, all of your operators
(such as "and" "or" "+") are functions with constant
inputs. As long as your types match the following is ok:

Y <= (A and B) or C ; -- calling or with result from and

Why did you find a bug here? The textio facility is
used much more than the built-in write function as
As a result, your vendor probably did not do alot of
compliance testing with it.

You are using the VHDL built-in write. Most
vendors probably do not do much testing in this
area as they expect people to be using the textio
read and write facilities using the file type text
(as it is the only one guaranteed to be ASCII).

Cheers,
Jim
P.S.
The only time I use the built-in write is for prompting
as the textio write/writeline always inserts a newline.
--
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Jim Lewis
Director of Training mailto:[email protected]
SynthWorks Design Inc. http://www.SynthWorks.com
1-503-590-4787

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