simulation result is correct but synthesis result is not correct

[J.Ram]

Hello,
I am having problem with a VHDL code, simulation was correct,
but when synthsized with synplify pro one port is connect, when i saw
RTL
view .

code is shown below
entity pn_clk is
port(
clk: in std_logic;
ref_clk : in std_logic;
reset : in std_log;
out_clk : in std_logic)

architecture behav of pn_clk is
signal sig_count : natural range 0 to 8 := 0;
begin
u1: process(clk, reset, ref_clk)
variable count : natural range 0 to 8 := 0;
begin
if reset = '1' or ref_clk = '1' then
count := 0;
end if;
if reset = '1' then
count := 0;
elsif rising_edge(clk) then
if count = 8 then
count := 0;
else
count := count + 1;
end if;
end if;
sig_count <= count;
end process u1;
u2: process(sig_count)
variable clk_var : std_logic := '0';
begin
if sig_count >= 4 or sig_count >5 then
clk_var := 0;
else
clk_var := 1:
end if;
clk_out <= clk_var;
end process u2;
end behav;

 

[Tricky]

There seem to be several errors here - I will go through line by line

code is shown below
entity pn_clk is
port(
clk: in std_logic;
ref_clk : in std_logic;
reset : in std_log;
out_clk : in std_logic)

You appear generating a clock generator using logic. If you are using
an FPGA I recommend that you DONT do this. You will cause yourself all
sorts of problems. Use DCMs (Xiling Digital clock manager) or PLLs
(altera Phase Lock Loops) to generate a /4 clock.

architecture behav of pn_clk is
signal sig_count : natural range 0 to 8 := 0;
begin
u1: process(clk, reset, ref_clk)
variable count : natural range 0 to 8 := 0;
begin
if reset = '1' or ref_clk = '1' then
count := 0;
end if;

What is this meant to do? I would completly remove it and leave it to
the reset below. The simulator can do whatever you tell it, but the
synthesisor has to generate logic as it sees fit. This is outside of
normal templates, so it is likely to confuse it, and generate
something sompletly unintentional.

if reset = '1' then
count := 0;
elsif rising_edge(clk) then
if count = 8 then
count := 0;
else
count := count + 1;
end if;
end if;

sig_count <= count;
end process u1;

This is the standard template. You should keep all variable/signal
assignments within the same if-the-else block.

u2: process(sig_count)
variable clk_var : std_logic := '0';
begin
if sig_count >= 4 or sig_count >5 then

The second case is already covered by the >= 4 statement

clk_var := 0;
else
clk_var := 1:
end if;

clk_out <= clk_var;
end process u2;
end behav;

Like I said before, if this is really a clock, then use a DCM or PLL
instead. Otherwise usethis as an enable to the intended registers, and
enable them only on 1 of the 9 counter states (did you really mean 9,
or 8? currently you will get a 5:4 mark space ratio on your clk_out) .
Clocking registers from logic-clocks is a big no no in FPGAs because
its easy to fail the timing requirements.

 

[olekk]

Hello,
I am having problem with a VHDL code, simulation was correct,
but when synthsized with synplify pro one port is connect, when i saw
RTL
view .

code is shown below
entity pn_clk is
port(
clk: in std_logic;
ref_clk : in std_logic;
reset : in std_log;
out_clk : in std_logic)

architecture behav of pn_clk is
signal sig_count : natural range 0 to 8 := 0;
begin
u1: process(clk, reset, ref_clk)
variable count : natural range 0 to 8 := 0;
begin
if reset = '1' or ref_clk = '1' then
count := 0;
end if;
if reset = '1' then
count := 0;
elsif rising_edge(clk) then
if count = 8 then
count := 0;
else
count := count + 1;
end if;
end if;
sig_count <= count;
end process u1;
u2: process(sig_count)
variable clk_var : std_logic := '0';
begin
if sig_count >= 4 or sig_count >5 then
clk_var := 0;
else
clk_var := 1:
end if;
clk_out <= clk_var;
end process u2;
end behav;

First: correct all syntax errors.

Second:
instead of

if reset = '1' or ref_clk = '1' then
count := 0;
end if;
if reset = '1' then
count := 0;

write:
if reset = '1' or ref_clk = '1' then
count := 0;

Third:
this
if sig_count >= 4 or sig_count >5 then
actually is equivalent to
if sig_count > 3 then
I suppose, this is not what was intended

Regards

 

[KJ]

Hello,
I have a problem in peice of code.
for simulation i used modelsim , and for synthesis synplify pro was
used.
when i do simulation with this code my functionality is achieved, but
during synthesis
one port (clk) is unconnected , when i saw result in RTL view.

Your posted code is riddled with typos and errors, it never made it
through a successful compile with Modelsim or Synplify let alone
actually simulating correctly. Clean up the code first, then run it
through and Modelsim and Synplify and then peruse any warnings that
Synplify might have and fix any issues that it may have and then come
back here and try again. Below are just some of the errors:

reset : in std_log;

std_log...when std_logic won't work, I guess std_log will

out_clk : in std_logic)

Will get back to 'out_clk' again later, but also note the lack of a
semicolon and the required 'end pn_clk;' statement to end the entity.

Given this declaration for clk_var...

variable clk_var : std_logic := '0';

Spot the errors in the following two assignments...

clk_var := 0;
clk_var := 1:

I guess you think 'clk_out' and 'out_clk' are the same thing or
something....no compiler will though.

clk_out <= clk_var;

Kevin Jennings

 

[J.Ram]

Your posted code is riddled with typos and errors, it never made it
through a successful compile with Modelsim or Synplify let alone
actually simulating correctly. Clean up the code first, then run it
through and Modelsim and Synplify and then peruse any warnings that
Synplify might have and fix any issues that it may have and then come
back here and try again. Below are just some of the errors:


std_log...when std_logic won't work, I guess std_log will


Will get back to 'out_clk' again later, but also note the lack of a
semicolon and the required 'end pn_clk;' statement to end the entity.

Given this declaration for clk_var...


Spot the errors in the following two assignments...


I guess you think 'clk_out' and 'out_clk' are the same thing or
something....no compiler will though.


Kevin Jennings

I have changed some errors , actually that was due to typing.
now code is synthesizable with clk is unconnected in RTL view, and
simulation is
correct which i needed.
this is clock divider circuit and used in FPGA , i can't use DCM
(xilinx ) because of
clock requirements.
i want to generate a free running clock which is divide by 9 of clk ,
and ref_clk is clk div by 576
and generated from anothrt part of code. now main purpose is to edge
alignment of div by 9 clock
with ref_clk.
code is mentioned below.
entity pn_clk is
port(
clk: in std_logic;
ref_clk : in std_logic;
reset : in std_logic;
out_clk : out std_logic)
end entity pn_clk;

architecture behav of pn_clk is
signal sig_count : natural range 0 to 8 := 0;
begin
u1: process(clk, reset, ref_clk)
variable count : natural range 0 to 8 := 0;
begin
if reset = '1' or ref_clk = '1' then
count := 0;
end if;
if rising_edge(clk) then
if count = 8 then
count := 0;
else
count := count + 1;
end if;
end if;
sig_count <= count;
end process u1;
u2: process(sig_count)
variable clk_var : std_logic := '0';
begin
if sig_count >= 4 then
clk_var := 0;
else
clk_var := 1:
end if;
out_clk <= clk_var;
end process u2;
end behav;

1. when i do following
if reset ='1' or ref_clk = '1' then
count := 0;
elsif clk'event and clk= '1' then
if count = 8 then
count := 0;
else
count := count +1;
end if;
sig_count <= count;
then my functionality is lost , at the time when ref_clk becomes high
(rising edge) sig_count becomes
0 two times.
please suggest different code , i need asynchronous reset only.
regards.

 

[KJ]

I have changed some errors , actually that was due to typing.

And you only have three remaining syntax errors still to fix, some
more typing required.

now code is synthesizable with clk is unconnected in RTL view, and
simulation is
correct which i needed.

As I mentioned in your comp.arch.fpga you didn't follow the template
for a flip flop so Synplify couldn't infer it. Refer to Synplify Help
VHDL Language Support/Sets and Resets/Asynchronous Sets and Resets for
the forms that it does support. Then make the following changes to
your code (in addition to fixing the three syntax errors)

if reset = '1' or ref_clk = '1' then
count := 0;
--KJ end if;
elsif rising_edge(clk) then

this is clock divider circuit and used in FPGA , i can't use DCM
(xilinx ) because of
clock requirements.

But does the fact that you're doomed to failure if you use these
divided clocks inside the FPGA to clock anything cause you any
concern?

i want to generate a free running clock which is divide by 9 of clk ,
and ref_clk is clk div by 576

And I'm assuming that you'll then use these divided clocks as the
clock input to some other code (i.e. if rising_edge(ref_clk) then).
If that's the case, then at best your design will be flaky and subject
to 'mysterious' occasional failures as a function of the temperature
of the part. At best, the design will flat out not work much at all
so you won't spend time waving heat guns and spraying cold spray.

Asynchronous clocking (i.e. using logic or flops to create clock
signals) inside an FPGA is one of the surest ways to dooming your
design...but of course it will work just fine in simulation...that's
when you learn about static timing analysis.

and generated from anothrt part of code. now main purpose is to edge
alignment of div by 9 clock
with ref_clk.

There is absolutely no way in an FPGA to guarantee any sort of
alignment between div by 9 clock and ref_clk. You will fail static
timing analysis assuming that you choose to perform this important
step.

Kevin Jennings

 

[Thomas Stanka]

Hello,

please suggest different code , i need asynchronous reset only.
regards.

Your task of a phase aligned clock divider in fpga is hard.
I would suggest you start with some simple designs to learn hardware,
static timing analyses and asynchronous timing domain crossings before
resuming on this project.

I showed you in comp.arch.fpga the correct template for a FF and you
didn't manage to use this simple template in reply to my posting,
because simulation with this template showed a behavior you didn't
like. But you can't do HW by squeezing code until it simulates correct
without having correct synthesisable code.

bye Thomas

 

[KJ]

On Dec 1, 6:43 pm, KJ <[email protected]> wrote:

1. when i do following
if reset ='1' or ref_clk = '1' then
count := 0;
elsif clk'event and clk= '1' then
if count = 8 then
count := 0;
else
count := count +1;
end if;
sig_count <= count;
then my functionality is lost , at the time when ref_clk becomes high
(rising edge) sig_count becomes
0 two times.
please suggest different code , i need asynchronous reset only.
regards.

Two suggestions:
1. Ditch the asynchronous resetting, most times it buys you absolutely
nothing and simply causes problems. Your inability to follow the
suggested templates is but one example of the types of problems one
can have with async resets (there are several others). Use a
synchronous reset form instead (see below).

2. Since you'll probably ignore #1 even though it is the better of the
two suggestions, use the proper form for an async reset. There are
two possible forms, see below.

Your code does not match either of the asynchronous forms so the
synthesizer does not recognize it as something to implement in flip
flops. It also presents a warning about combinatorial logic loops
that should be a clue that it is lost.

-- Synchronous form
if rising_edge(clock) then
if reset_condition then
-- Put your reset stuff here
else
-- Put your synchronous stuff here.
end if;
end if;

-- Async form #1
if reset_condition then
-- Put your async reset stuff here
elsif rising_edge(clock) then
-- Put your synchronous stuff here.
end if;

-- Async form #2
if rising_edge(clock) then
-- Put your synchronous stuff here.
end if;
if reset_condition then
-- Put your async reset stuff here
end if;

Kevin Jennings