simulation stops preliminarily

V

Valentin Tihomirov

this code causes 100% simulation failure.

Rx <= '1'; wait for 1 * BIT_TIME; -- initialize a bit value

assert (Rx = '0') -- fail if bit = '1'
report "Invalid data received1!"
severity failure;

assert (Rx = '1') -- fail if bit = '0'
report "Invalid data received2!"
severity failure;

wait until AVAIL = '1';

wait; -- will wait forever





I need to check a vaue after AVAIL rises to '1'. But the following test
shows that simulator ignores ASSERT clauses placed between WAIT forever
statement.

Rx <= '1'; wait for 1 * BIT_TIME; -- initialize a bit value

wait until AVAIL = '1'; -- wait for condition


-- these assertions are ignored by simulator!

assert (Rx = '0') -- fail if bit = '1'
report "Invalid data received1!"
severity failure;

assert (Rx = '1') -- fail if bit = '0'
report "Invalid data received2!"
severity failure;

wait; -- will wait forever




Does ModelSim behaves properly?
 
J

Jonathan Bromley

I need to check a vaue after AVAIL rises to '1'. But the following test
shows that simulator ignores ASSERT clauses placed between WAIT forever
statement.

Rx <= '1'; wait for 1 * BIT_TIME; -- initialize a bit value

wait until AVAIL = '1'; -- wait for condition


-- these assertions are ignored by simulator!

assert (Rx = '0') -- fail if bit = '1'
report "Invalid data received1!"
severity failure;

assert (Rx = '1') -- fail if bit = '0'
report "Invalid data received2!"
severity failure;

wait; -- will wait forever

Are you 100% sure that AVAIL is making a transition to '1'
at some time after the previous wait has finished?

Don't forget that "wait until" is EDGE triggered. It
will wait forever if AVAIL is stuck at '1'.
--
Jonathan Bromley, Consultant

DOULOS - Developing Design Know-how
VHDL * Verilog * SystemC * Perl * Tcl/Tk * Verification * Project Services

Doulos Ltd. Church Hatch, 22 Market Place, Ringwood, Hampshire, BH24 1AW, UK
Tel: +44 (0)1425 471223 mail: (e-mail address removed)
Fax: +44 (0)1425 471573 Web: http://www.doulos.com

The contents of this message may contain personal views which
are not the views of Doulos Ltd., unless specifically stated.
 
J

Jim Lewis

I need to check a vaue after AVAIL rises to '1'.
Don't forget that "wait until" is EDGE triggered. It
will wait forever if AVAIL is stuck at '1'.

And to add to what Jonathan said, if you want to do a
level check, do the following:

if (Avail /= '1') then
wait until AVAIL = '1';
end if ;


Read wait as stop.
Wait always stops for at least one delta cycle.

Cheers,
Jim
--
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Jim Lewis
Director of Training mailto:[email protected]
SynthWorks Design Inc. http://www.SynthWorks.com
1-503-590-4787

Expert VHDL Training for Hardware Design and Verification
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
 

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