- Joined
- Oct 20, 2009
- Messages
- 1
- Reaction score
- 0
Hello.
Any difference?
Code:
signal slv : std_logic_vector(1 downto 0);
signal s1,s2 : std_logic;
process()
begin
s1 <= '0';
s2 <= '0';
-----------------
--
-- Version with 'elsif'
--
if(slv = "00") then
s1 = '1';
elsif (slv = "10") then
s2 = '1';
end if;
-----------------
--
-- Version without 'elsif'
--
if (slv = "00") then
s1 <= '1';
end if;
if (slv = "10") then
s2 <= '1';
end if;
-----------------
end process;
Any difference?
Last edited: