Some System Verilog questions

[sundar]

Since there is no separate sysetm verilog discussion group I am
posting my queries on System verilog here.
1. Is there a way to use System verilog in VHDL configuration file?
for example.
file1: d_flipflop.vhd is a vhdl file with a simple d-flip flop design
file2: d_ff_testbench.sv is a system verilog file which calls DUT
(d_flipflop.vhd). But instead of passing clock generated within this
test bench , I have a input clock for this d_ff_testbench.sv.
file3: clock_gen.vhd is a vhdl file which has a clock output
file4: config.vhd is a vhdl file which actually configures the clock
out of clock_gen.vhd to clock in of d_ff_testbench.sv. If this is
achieved then the clock in d_ff_testbench.sv will pass the value of
clock to d_flipflop.vhd (DUT)
please tell me whether the above approach is possible(i have created
all files. no errors while compiling or simulating in questasim but
the clock out from clock_gen.vhd is not passed to clock in of
d_ff_testbench.sv)

2. Is there a way to invoke PERL modules thru system verilog?
as for as my understanding we can use $system in system verilog but
this is not solving my purpose.
I have a perl file "myperl.pl" which actually reads a input.txt file
and generates output.txt. while executing this file i use command "
perl myperl.pl -i input.txt -o output.txt write 5". here i use "write"
or "read" because i have sub programs/functions in my perl which gives
ouput according to the switch "read" or "write" and also generates
according to number switch "5" or "6" or "n". my requirement is I need
to use "write(5)" in my system verilog test bench which should invoke
the "myperl.pl" and create output.txt as per it is designed.


thoughts on the above scenarios are welcomed.

regards,
Sundar