N
Niv
I have to interface several DACs, ADCs and temp sensors (all different
mnfrs of course) to an FPGA.
Now, the data sheets all say they are SPI compatible.
All seem to have a serial clock and chip select input.
The DACs have serial data input,
the ADCs have serial data output,
the temp sensor has a single data I/O pin!
Now the SPI spec seems to sort of agree (not with single I/O pin
though).
I need to write some VHDL that'll handle all the above, so I have a
common module,
in, out & I/O controlled by generics probably (as well as max clock
speed).
The VHDL block will be the master, controlled via our in-house common
bus structure from
a remote(ish) processor
Anyone point me at some SPI clarification please?
(Or I could be greedy & ask for pre-written example to start me off).
Regards, Niv.
mnfrs of course) to an FPGA.
Now, the data sheets all say they are SPI compatible.
All seem to have a serial clock and chip select input.
The DACs have serial data input,
the ADCs have serial data output,
the temp sensor has a single data I/O pin!
Now the SPI spec seems to sort of agree (not with single I/O pin
though).
I need to write some VHDL that'll handle all the above, so I have a
common module,
in, out & I/O controlled by generics probably (as well as max clock
speed).
The VHDL block will be the master, controlled via our in-house common
bus structure from
a remote(ish) processor
Anyone point me at some SPI clarification please?
(Or I could be greedy & ask for pre-written example to start me off).
Regards, Niv.