SPI Problem

[Fizzy]

Hi,

I am trying to interface Virtex4FX FPGA with a device over SPI. I am
new to SPI and FPGA. While reading through the documents i found below
statement which i could not understand. Please any one help me out....

"You will want to analyze the FPGA setup/hold time relative to the SCLK
output"

I have a 3-wire (SCLK, SPI_DATA and CS) SPI controller implemented on
FPGA and SCLK is running at 2 MHz. I want to receive the data over SPI
from the device into FPGA and there i got problem as i stated above.

Thanks for helping

 

[asicbaba]

hi buddy,

in general the spi will have one serial in , one serial out and clock
with cs pin...now in ur cases with respect ur implementation u got
single data in and data out line.....

now fr every every input port and every output port there will eb
constrains u have to gv with respect to ur external spi device
specifications.....

now read the data sheet of the device and see the set and hold
requirement of teh device and apply them as constraints fr ur FPgA and
resynthesize and p & R....then u run it will work....

 

[Fizzy]

Thanks for replying.....

I have DEI 1067 device connected to FPGA and its data sheet can be
found on http://www.deiaz.com/data-sheets/DS-MW-01067-01-B.pdf.
I understand your explanation but when i revisited the data sheet i was
confused i as i was. On page 8 they have a lot of timing variables and
on page 9 they have a timing diagram. Which variable should i consider
while designing SPI controller on FPGA. I though all i had to do is to
send a SCLK on output and sample in the data comming from the device
without considering any of the timming given on page 8 of data sheet.
All these timming are given for the Device DEI1067... Is not that true?

 

[Andrew FPGA]

Using common naming conventions, your average flip flop has a D(data)
input, a Q output and a clock input.
At the active clock active edge(say rising edge) the D input is sampled
and this sampled value is driven to the Q output. If the D input
changes value "near" this clock edge then one cannot know if the Q
output will go high or low.

In order to be certain that the D input will propagate to the Q output
the D input must be stable a "setup" time before the active clock egde,
and the D input must remain stable a certain "hold" time after the
clock edge.

Regards
Andrew

 

[Andrew FPGA]

If you want this to be a reliable design, you need to read, understand
and ensure your design meets all of those parameters on pg 8.