SRAM "Hread" problem

[comeonqq]

When I compilate SRAM in VHDL by Quatus II, there is error in use IEEE.STD_LOGIC_TEXTIO.all; I found "hread" is invalid in library.
Does anyone know how to solve this problem?

If anyone work on the USB host by VHDL, please give some advise. It's so difficult. Thank you.
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Error (10800): VHDL error at SRAM.vhd(29): selected name in use clause is not an expanded name

library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.STD_LOGIC_UNSIGNED.all;
use IEEE.STD_LOGIC_ARITH.all;
use IEEE.STD_LOGIC_TEXTIO.all;

library STD;
use STD.TEXTIO.all;

entity SRAM is
generic (
fname: STRING); -- path to intel hex file
port(
A: in STD_LOGIC_VECTOR(14 downto 0); -- address bus
D: inout STD_LOGIC_VECTOR(7 downto 0); -- data bus
CE: in STD_LOGIC; -- chip enable
OE: in STD_LOGIC; -- output enable
WE: in STD_LOGIC -- write enable
);
end SRAM;

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architecture Sim of SRAM is
type Tmem is array (0 to 4096) of STD_LOGIC_VECTOR (7 downto 0);
signal mem: Tmem;
begin

process(A, D, CE, OE, WE)

procedure hexrecord(


constant fname: in STRING;
signal mem: out Tmem) is
file hexfile: TEXT open READ_MODE is fname;
variable linebuf: LINE;
variable char: CHARACTER;
variable nibble: STD_LOGIC_VECTOR( 3 downto 0);
variable count: STD_LOGIC_VECTOR( 7 downto 0);
variable addr: STD_LOGIC_VECTOR(15 downto 0);
variable byte: STD_LOGIC_VECTOR( 7 downto 0);
variable check: STD_LOGIC_VECTOR( 7 downto 0);
begin
while not endfile(hexfile) loop
readline(hexfile, linebuf);
if linebuf'length> 8 then
-- read ':'
read(linebuf, char);
-- read count
hread(linebuf, nibble); count( 7 downto 4):= nibble;
hread(linebuf, nibble); count( 3 downto 0):= nibble;
-- read address
hread(linebuf, nibble); addr(15 downto 12):= nibble;
hread(linebuf, nibble); addr(11 downto 8):= nibble;
hread(linebuf, nibble); addr( 7 downto 4):= nibble;
hread(linebuf, nibble); addr( 3 downto 0):= nibble;
-- skip 00
hread(linebuf, nibble);
hread(linebuf, nibble);
-- read bytes
for i in 1 to CONV_INTEGER(count) loop
hread(linebuf, nibble); byte(7 downto 4):= nibble;
hread(linebuf, nibble); byte(3 downto 0):= nibble;

mem(CONV_INTEGER(addr))<= byte;

addr:= addr + 1;
end loop;
-- read checksum
hread(linebuf, nibble); check(7 downto 4):= nibble;
hread(linebuf, nibble); check(3 downto 0):= nibble;
end if;
end loop;
end procedure;

variable initmem: BOOLEAN:= TRUE;

begin

if initmem then
write( output, "SRAM initialization...." );
hexrecord(fname, mem);
initmem:= FALSE;
else
if CE= '0' then
if WE= '0' then
mem(CONV_INTEGER(A))<= D;
-- assert FALSE
-- report "write access to SRAM!"
-- severity FAILURE;
end if;

if OE= '0' then
D<= mem(CONV_INTEGER(A));
else
D<= (others=> 'Z');
end if;
end if;
end if;
end process;

end Sim;