Can I use 'stable operator in VHDL to monitor the change of signal level without using it as clock signal.
Signal a : std_logic;
begin
process ()
If rising_edge (clk) then
if (not a'stable) then
Dout <= Din;
end if;
end if;
But this gives me error in xilinx ISE and I had to use the stable operator as clock signal like,
if (not a'stable and a='1')
any guidelines of how to use 'stable operator
Signal a : std_logic;
begin
process ()
If rising_edge (clk) then
if (not a'stable) then
Dout <= Din;
end if;
end if;
But this gives me error in xilinx ISE and I had to use the stable operator as clock signal like,
if (not a'stable and a='1')
any guidelines of how to use 'stable operator