Yes 'pos and 'val synthesize ok for constrained values.
But some days, I don't like the looks of:
case my_type_t'val( to_integer(unsigned(adr))) is ...
I have run into this issue when writing code
for an interface with a predefined address slice encoding.
Let's say:
type my_type_t is (load, auto, nom, cal); -- published modes
-- 00 01 10 11 -- published values
In this case, I might write a function like
this to tidy up the mess:
function vec2mode (arg : std_logic_vector)
return my_type_t is
variable argn_v : natural := to_integer(unsigned(arg));
begin
return my_type_t'val(argn_v);
end function vec2mode;
And use it like this:
procedure update_regs is
begin
if wr = '1' then
case vec2mode(adr) is
when load => do_load;
when cal => do_cal;
when nom => do_nom;
when auto => do_auto;
when others => do_nom;
end case;
end if;
end procedure update_regs;
-- Mike Treseler
Hi Mike,
It looked like Niv wanted/had a "sequential" state machine
implementation and wanted a state vector to output to testpoints. It
seemed that if his implementation looked something like below, the
test state vector could be added in about one line of VHDL. When I
looked at the simplified circuit through the technology viewer, the
state_vec was directly tapped off the output of the state machine flip
flops when the synthesizer was directed to use a sequential
implementation.
I have never before used the pos attribute in synthesizable code,
but had an idea and wanted to see if it would pan out. Mike, I enjoy
your posts, because I view you as a craftsman and in general, your
style is much different from mine.
-Newman
------------------------------------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity state_test is
port (
clk : in std_logic;
reset : in std_logic;
state_vec : out std_logic_vector(1 downto 0)
);
end state_test;
architecture behav of state_test is
type state_typ is (state_0, state_1, state_2, state_3);
signal state : state_typ := state_0;
begin -- behav
-- concurrent
state_vec <=
std_logic_vector(to_unsigned(((state_typ'pos(state))),state_vec'LENGTH));
sync_proc : process (clk, reset)
begin -- process sync_proc
if reset = '1' then
state <= state_0;
elsif clk'event and clk = '1' then
case state is
when state_0 => state <= state_1;
when state_1 => state <= state_2;
when state_2 => state <= state_3;
when state_3 => state <= state_0;
when others => null;
end case;
end if;
end process sync_proc;
end behav;
