State machine glitch

[yaseenzaidi]

I have a state machine that sets an output high in a state (1) and in
the next state (2) I like the same output to be high asserted
synchronously with an enable. To overt a latch inference I explicitly
set the output high in (2). Since the output is high in both (1) and
(2), right at the state transition clock edge there is an
infinitesimally diminutive spike as if in (2) the output going from low
to high while it was already high. This pulse would not meet the setup
and hold time requirement for the FPGA flip flop. What are your
suggestion about removing output glitches at state transitions.

Regards,

YZ

 

[Mike Treseler]

What are your
suggestion about removing output glitches at state transitions.

Please post the vhdl code if you want comments on it.

-- Mike Treseler

 

[Thomas Stanka]

Hi,

I have a state machine that sets an output high in a state (1) and in
the next state (2) I like the same output to be high asserted
synchronously with an enable. To overt a latch inference I explicitly
set the output high in (2). Since the output is high in both (1) and
(2), right at the state transition clock edge there is an
infinitesimally diminutive spike as if in (2) the output going from low
to high while it was already high. This pulse would not meet the setup
and hold time requirement for the FPGA flip flop. What are your
suggestion about removing output glitches at state transitions.

Is this problem observable during simulation (rtl or on netlist) or on
fpga?
And what is your exact problem with this spike? A typical solution
would be the usage of an register for your output. Spikes on FF inputs
have no influence, unless your spike is within setup/hold time for the
clockedge.

There exist technics to remove spikes, like inserting of redundant
logic. If you have a simple circuit and draw a kv-diagramm you could
add additional minterms for example
(Don't use this sollution unless you know what you are doing).

bye Thomas

 

[Peter]

Hi,

Without the code it's difficult to answer, but one mistake could be to
assign the output outside the synchronous process.

/Peter

 

[radarman]

Register the outputs of the state machine. This will guarantee
glitch-free outputs.

For example:

entity FSM_Demo is
port(
Clock : in std_logic;
Reset_n : in std_logic;
Input : in std_logic;
Output : out std_logic );
end entity;

architecture rtl of FSM_Demo is
type FSM_STATES is ( IDLE, STATE_A, STATE_B );
signal State_D, State_Q : FSM_STATES;
signal Output_D, Output_Q : std_logic;
begin

Output <= Output_Q;

S_Regs: process( Reset_n, Clock )
begin
if( Reset_n = '0' )then
State_Q <= IDLE;
Output_Q <= '0'
elsif( rising_edge(Clock) )then
State_Q <= State_D;
Output_Q <= Output_D;
end if;
end process

FSM : process( State_Q, Input )
begin
State_D <= State_Q
Output_D <= '0';

case State_Q is
when IDLE =>
if( Input = '1' )then
State_D <= STATE_A;
when STATE_A =>
State_D <= STATE_B;
Output_D <= '1';
when STATE_B =>
State_D <= IDLE;
Output_D <= '1';
when others =>
null;
end case;
end process;

end rtl;