Hi group!
I am studing VHDL and I have read in a .ppt presentation that it better to use the std_match function from the numeric_std IEEE library for comparing instead of using ‘=‘ (For example:
if(std_match(bi_value,'0') then
and not
if(bit_vale='0') then
)
because this guarantees that we will get the same results in simulation and
synthesis.
But I don't understand this assertion: it's right and why?
Can someone helps me???
Tnx to all
I am studing VHDL and I have read in a .ppt presentation that it better to use the std_match function from the numeric_std IEEE library for comparing instead of using ‘=‘ (For example:
if(std_match(bi_value,'0') then
and not
if(bit_vale='0') then
)
because this guarantees that we will get the same results in simulation and
synthesis.
But I don't understand this assertion: it's right and why?
Can someone helps me???
Tnx to all