Hey,
I have two input signals at the beginning of my design. Simple std_logic inputs with pretty similar frequencies. Up until now I've just been using a flip flop, the output with a frequency of f1-f2.
This works without problems until the frequencies get within 0.5% of each other. (I guess due to jitter)
After that I implemented something along the lines of:
if rising_edge (f1) then
Qrise <= f1;
end if;
invf1 <= not f1;
if rising_edge (invf1) then
Qfall <= not f1;
end if;
Q <= Qfall or Qrise;
This increased the working range down to about 0.35% of f1.
The problem is that I need to have something which works better than that. I guess something in the line of phase locked loops (?), but honestly I have no idea how to work with that.
I'd really appreciate any small help here. (and if the hardware is important here I can look up the exact tools I'm using and post them later)
I have two input signals at the beginning of my design. Simple std_logic inputs with pretty similar frequencies. Up until now I've just been using a flip flop, the output with a frequency of f1-f2.
This works without problems until the frequencies get within 0.5% of each other. (I guess due to jitter)
After that I implemented something along the lines of:
if rising_edge (f1) then
Qrise <= f1;
end if;
invf1 <= not f1;
if rising_edge (invf1) then
Qfall <= not f1;
end if;
Q <= Qfall or Qrise;
This increased the working range down to about 0.35% of f1.
The problem is that I need to have something which works better than that. I guess something in the line of phase locked loops (?), but honestly I have no idea how to work with that.
I'd really appreciate any small help here. (and if the hardware is important here I can look up the exact tools I'm using and post them later)