Synchronizing logic to a clock egde

[lloyd.rochester]

I am trying to make a deserializer in VHDL. Serialized data comes in
frames as you would imagine. There are 14 serialized bits in one word,
7 of them are when the frame signal is high, 7 are then the frame
signal is low, then another 14-bit word is sent. On the rising edge of
the frame signal I start a counter and take the serialized bits and put
them into a std_logic_vector, with the counter being the index to a
std_logic_vector(13 downto 0). Everything works fine with this
deserializer except, a synchronization problem. I need this thing to
start deserializing when it detects the first rising edge of the frame
signal. The only problem I have with the code below is the start
std_logic does not seem to start the counter correctly. I need the
start std_logic to have a value '0' initially, and be '1' on the first
rising edge of the clock, and stay that way forever. Serial data is
sampled on the rising edge of serial_clock, and there are 14
serial_clock periods for 1 frame_clock period.

entity deserializer is
port(serial_clock : in std_logic; frame_clock : in std_logic;
serial_data : in std_logic, data : out std_logic_vector(13 downto 0));
end deserializer

architecture deserializer_architecture of deserializer is
signal bitcnt : unsigned(4 downto 0) := "00000"; --14 bits in one word
signal start : std_logic := '0';
begin
frame_process: process(frame_clock)
begin
if (frame_clock'EVENT and frame_clock = '1') then
start <= '1';
end if;
end process frame_process;
deserializing_process: process(serial_clock)
begin
if (serial_clock'EVENT and serial_clock = '1' and start = '1')
then
data(to_integer(bitcnt)) <= serial_data;
bitcnt <= bitcnt +1;
if (bitcnt = 13) then
bitcnt <= "00000";
data <= "00000000000000";
end if;
end if;
end process deserializing_process;
end deserializing_process;

Forgive me if there is a slight error it just typed it in, it is not
my exact code.

To the ones of you that see an obvious flaw with my logic please
respond to this topic. I want to start my deserializing process on the
first rising edge or frame_clock, and have the counter say initalized
to zero until this even happens. If I don't start my logic on this
first rising edge then my counter will be off and I will serialize the
bits wrong. Is there a better way of doing this?

Thanks

 

[Mike Treseler]

To the ones of you that see an obvious flaw with my logic please
respond to this topic.

This is a good example of why I prefer
variables to signals for describing logic.
Your condition (bitcnt = 13) uses the bitcnt value
from the *previous* loop despite the increment on
the line above.

Is there a better way of doing this?

1. Learn how to use a vhdl simulator so
that you will be able to do your own debugging.

2. I use variables so that all values described
in the process are *present* values.
Look here for some design examples:

http://home.comcast.net/~mike_treseler/

-- Mike Treseler

 

[homoalteraiensis]

This is a typical "error" of people coming from the C/C++ domain.
Testing a recently changed signal only works in parts outside the
clockedge process. Doing it this way would require a concurrent signal
handling like (here) "if bitcount = 12" since the test of ending is
done one clock edge too late, in reality.

Variables are one way to shun this problem. Using two signals (an "is"
one and a "new" one after clock edge)helps to distinguish the two time
zones in cases both states of the signals are required.