Synplify - Init Rom from file - Howto?

[dkbauter]

Hi,

currently I'm trying to synthesize a project (including a ROM) on a Spartan3
FPGA.
I've to initialize the ROM with a text file (from a Sys-C Co-simulation).
Unfortunatelly the initialization seems not to work using the synplify compiler.

The VHDL code I'm using is quite similar to this (see also _www_.xilinx.com/itp/xilinx8/books/data/docs/xst/xst0027_5.html#wp657988 - Initializing RAM from an External File):

architecture rtl of rom_vhdl is 
	type RomType is array(0 to 7) of bit_vector(31 downto 0); 
	
	impure function InitRomFromFile (RomFileName : in string) return  RomType is 
		FILE RomFile : text is in RomFileName; 
		variable RomFileLine : line; 
		variable ROM : RomType; 
	begin 
		for I in RamType'range loop 
		readline (RamFile, RamFileLine); 
		read (RamFileLine, RAM(I)); 
		end loop; 
		return ROM; 
	end function; 

	signal ROM : RomType := InitRomFromFile(a_generic_file_name); 	
	begin
	   ...
	end rtl;

Alltough it compiles and works fine simulating with Modelsim, I can't
compile it with Synplify.

The compiler always quits with the error message "@E:CD541 Expecting ;".
The concerned line is "FILE RomFile : text is in RomFileName;". However, the
syntax is OK.
My first intention was, that the synplify compiler is not able to work with
such a VHDL87 language construct. Nevertheless changing to syntax to
VHDL93 doesn't help.

Any ideas? Thanks!

 

[dkbauter]

Here a short update:
It seems that Synplify Pro (v9.4) doesn't support the textio87 package.

When using

 FILE RomFile : text is in RomFileName;

I'm getting the error message "identifier RomFile is unknown".

On the other hand if I'm using a VHDL93 compliant version

 file RomFile : text open read_mode is RomFileName; --vhdl 93 only

the file is accessible.

Nevertheless reading the file leads to another error since the compiler reads "past end of file".
Since there are a few comments within the file I've to parse the file until its end

 VHDL87: while not(endfile(RomFile)) loop ... end loop;

But it seems that the synplify compiler ignores the endfile construct since it isn't supported in VHDL93.
Using a query like

 if RomFileLine'length = 0 then ...

doesn't work, too.

As I can remember synplify in general doesn't allow the usage of the textio packages. However,
the previously listed code is an official Xilinx template beeing automatically synthesized into a singe port block ram
(or something similar ). So I expected it could also work using the Synplify Tool. Everything works fine when I'm compiling (with
Mentor Compiler) and simulating with Modelsim/Questasim. Only Synplify can't handle the assignments.

As mentioned the file comes from a co-simulation. Since it isn't finished yet, I've to start the flow with a "primitive" version
of the rom code and re-synthesize it step by step.
So it would be an enormous simplification just importing the rom file automatically within the vhdl code.
Anyone else dealing with such a problem?