synthesis and sensitivity list?

[Elinore]

Hi

In the FSM example below, sensitity list is supposed to be (clk,
reset).

What if (clk, reset, input) ?

How is differently synthesized, for example, in Xilinx FPGA synthesis
tool, XST?

process(clk,reset)
begin
if (reset='1') then
state <= S1;
output <= '1';
elsif(clk='1' and clk'event) then
case state is
when s1 =>
if input ='1' then --- FSM input
state <= s2;
output <= '1';
else
state <= s3;
output <= '0';
when s2 => state <= s4; output <= '0';
end case;
end if;
end process

 

[Peter]

The process is only triggered on clk and reset, so "input" shall not be
in the sensitivity list. That is the normal case for a synchronous
design with asynchronous reset.
Synthesis programs does not care about sensitivity list but gives you a
warning if they are not complete.

/Peter

 

[Neo]

If you put "input" also in the sensitivity list it dosent matter for
the synthesis tool but it will usually give warnings. But you will end
up with simulation synthesis mismatch as simulation will take into
account your sensitivity list.

 

[Ralf Hildebrandt]

In the FSM example below, sensitity list is supposed to be (clk,
reset).

What if (clk, reset, input) ?

How is differently synthesized, for example, in Xilinx FPGA synthesis
tool, XST?

process(clk,reset)
begin
if (reset='1') then
state <= S1;
output <= '1';
elsif(clk='1' and clk'event) then ....
end process

If you add any signal, the process will be triggered, if an there is an
'event of the added signal, but nothing will happen, as the two
if-clauses are false. -> Just unnessecary overhead for simulation, but
no false behavior for simulation or synthesis.

Note, that this behavior is because of the rising-edge dectection. For
combinational logic or latches you have to take more care with the
sensitivity list.

Ralf

 

[Rob Dekker]

If you put "input" also in the sensitivity list it dosent matter for
the synthesis tool but it will usually give warnings. But you will end
up with simulation synthesis mismatch as simulation will take into
account your sensitivity list.

Actually it is totally benign to put more signals on the sensitivity list than need.
Synthesis tool only warns if there are signals MISSING, because this would
lead to synthesis/simulation mismatches.

Synthesis / simulation results are the same, if there are EXTRA signals on the list.

Rob

 

[Mike Treseler]

Rob Dekker wrote

Synthesis / simulation results are the same, if there are EXTRA signals on the list.

The duration of the simulation run
and the clarity of the code
are not the same.


-- Mike Treseler

 

[Ahmed Samieh]

Hi

In the FSM example below, sensitity list is supposed to be (clk,
reset).

What if (clk, reset, input) ?

How is differently synthesized, for example, in Xilinx FPGA synthesis
tool, XST?

http://www.doulos.com/knowhow/vhdl_designers_guide/if_statement/

Sensitivity list
It is a fundamental rule of VHDL that only signals (which includes input and buffer ports) must appear in the sensitivity list.


Golden Rule 1:
To synthesize combinational logic using a process, all inputs to the design must appear in the sensitivity list.

!!!

Ahmed Samieh