synthesis question of fixed point library

[sanborne]

I am having a problem synthesizing a design where I utilized David
Bishop's fixed point library extensively. There might be 2 causes to
this problem and I am hoping there is someone out there who can help.

First of all I am using the Xilinx 10.1 webpack. I am not sure if the
fixed point library will work with this free synthesis tool. I could
get a commercial license if necessary, but I have not read in any of
the documentation where it explicitly states that I need the
commercial product.

Second, I am wondering if I am attempting to synthesize the wrong
file. The error that I am getting is "HDLParsers:1014 - "//infnas-00-
ah/slittle/Projects/redesign/custom_vhdl/zigg_synth/
standard_additions_c.vhdl" Line 1884. Allocators unsupported." I did a
search in this newsgroup for the above error, and I found a thread
that seems to indicate that "allocators" are the VHDL equivalent of
dynamic memory allocation, which is impossible in hardware synthesis.
So the question is what should I do? Is there another version of
"standard_additions_c.vhdl" that I should be using? Where could I get
that a copy of the fixed point library that is synthesizable? I
suspect that I would need a whole different library, because if
"standard_additions_c.vhdl" has a synthesis error, then the other
files that I am referencing will also.

Is there another reason that I might be getting this error? I
appreciate any insight.

SY

 

[sanborne]

Xilinx didn't used to support negative indices for vectors which are
required in order to implement the fixed point lib stuff since negative
indices are used for the 'fractional' part of the representation.  I've
heard Xilinx will be supporting it and maybe 10.1 does.




For the fixed point package you only need the files 'fixed_pkg_c.vhdl' and
'math_utility_pkg.vhdl' source files.  The file 'standard_additions_c.vhdl'
does have allocators, it is not synthesizable, but you shouldn't need to use
it either.  Per the comments in the 'standard_additions_c.vhdl' file...
-- "standard_additions" package contains the additions to the built in
-- "standard.std" package.  In the final version this package will be
implicit.
--  Created for VHDL-200X par, David Bishop ([email protected])

But if you peruse the source file 'fixed_pkg_c.vhdl' you'll see that the
only other package dependencies are:
-- use ieee.std_logic_1164.all;
-- use ieee.numeric_std.all;
-- use ieee_proposed.math_utility_pkg.all;
-- use ieee_proposed.fixed_pkg.all;


Don't use that file for synthesis, it is not needed to implement fixed
point.

Kevin Jennings

Ok, this is really frustrating. I finally was able to get access to
Synplify-Pro (version 8.6.2), thinking that after all the issues I had
with Xilinx, I would finally be able to synthesize my project. But
there seem to be compilation errors in Synplify! I have searched this
group, and I am definitely not the only person who has had this
problem, but no one has posted an answer this question. See:
http://groups.google.com/group/comp...gst&q=ieee_proposed+synplify#4738601448b04a5a
http://groups.google.com/group/comp...plicate+definition+fixed_pkg#14d7f8ae3fa069e2

I am new to using Synplicity products, and maybe I am doing something
terribly and trivially wrong, but I sure can't figure out what the
problem is...

Steps:

1) Downloaded the Synplicity version of the fixed point library from:
http://www.eda-stds.org/fphdl/synplicity.zip

2) Create a new project in Synplify and load my VHDL files.
I set my top level entity name under Options->Configure VHDL Compiler,
and select the VHDL tab.

3) Add the following files from the downloaded Synplicity library:
math_utility_pkg_c.vhdl
fixed_pkg_c.vhdl

The files above are set to the library ieee_proposed using the Project-

Set VHDL Library option.

4) When compiling the project, I get the following compilation errors
(copied from the compilation log file):
@I:: "H:\Projects\redesign\custom_vhdl\synplicity_fp\fixed_pkg_c.vhdl"
@E: CD415 :"H:\Projects\redesign\custom_vhdl\synplicity_fp
\fixed_pkg_c.vhdl":1164:61:1164:61|Expecting keyword return
@E: CD428 :"H:\Projects\redesign\custom_vhdl\synplicity_fp
\fixed_pkg_c.vhdl":1460:21:1460:21|Duplicate definition of package
fixed_pkg
@E: CD200 :"H:\Projects\redesign\custom_vhdl\synplicity_fp
\fixed_pkg_c.vhdl":8086:4:8086:13|Misspelled variable, signal or
procedure name?
@E: CD415 :"H:\Projects\redesign\custom_vhdl\synplicity_fp
\fixed_pkg_c.vhdl":8607:26:8607:26|Expecting keyword is
4 errors parsing file H:\Projects\redesign\custom_vhdl\synplicity_fp
\fixed_pkg_c.vhdl

This is going to be a huge bummer if I cannot get this code to
synthesize. I would really appreciate any pointers from anyone.

Thanks,

SY

 

[Mike Treseler]

@E: CD428 :"H:\Projects\redesign\custom_vhdl\synplicity_fp
\fixed_pkg_c.vhdl":1460:21:1460:21|Duplicate definition of package
fixed_pkg

Sounds like you included code for fixed_pkg twice,
or synplicity already knows about it.

-- Mike Treseler

 

[sanborne]

Sounds like you included code for fixed_pkg twice,
or synplicity already knows about it.

     -- Mike Treseler

So I figured out the problem. I updated to Synplify 9.6.2, and the
design synthesized successfully.

Is it normal that there are 62 warnings produced in the
fixed_pkg_c.vhdl file? I have learned not to just ignore warnings when
synthesizing hardware.

SY

 

[Mike Treseler]

So I figured out the problem. I updated to Synplify 9.6.2, and the
design synthesized successfully.

Did it sim successfully?

Is it normal that there are 62 warnings produced in the
fixed_pkg_c.vhdl file?

Like you said, you may be the first to have tried this.
Talk to the package author, and to the synthesis vendor.

-- Mike Treseler