synthesizable Generic Mux

[slvador]

Hello

i am trying to make a generic mux that takes any number of inputs, input width and number of selectors. i have the following code. it works in sumulation, but when i try to synthesize it, VHDL issue a warning about a width mismatch. and for some reason, it takes all the memory to synthesize it, so i run out of memory error. which is 2 gigs. i am trying to use a big mux with 138 input width and 8 select pins. i try to reduce number of inputs, but that didn't work. here is the code for my generic mux

entity gen_mux is generic (noInputs : integer :=8; input_width : integer := 32; select_Pins : integer :=3);
Port ( inputs : in STD_LOGIC_VECTOR(noInputs * input_width -1 downto 0);
sel : in STD_LOGIC_VECTOR(select_Pins -1 downto 0);
output : out STD_LOGIC_VECTOR(input_width -1 downto 0));
end gen_mux;

architecture Behavioral of gen_mux is

begin


output <= inputs((CONV_INTEGER(sel)+1)*input_width-1 downto CONV_INTEGER(sel)*input_width );

end Behavioral;

the bold sentence is the important one. it is a very simple way to do it. i think the problem is the CONV_INTEGER, but i don't know how to substitute it with something else

If any got any input, please

 

[jeppe]

Hi

I tried this myself, but your right .. the code surely gives the synthesize tools problems.
However seems the code below to work ok.

begin
   process( Sel, Inputs)
	   variable Hi_index,Lo_index: integer range 0 to 255;
	begin
		Lo_index :=   CONV_INTEGER(sel)*input_width;	
		Hi_index :=   Lo_index+input_width-1;
		output <= inputs( Hi_index downto Lo_index);
   end process;
end Behavioral;

Your welcome
Jeppe