Target type ieee.std_logic_1164.std_ulogic in signal assignment isdifferent frim expression type std

[Diego UTN-FRP]

Hello people.
Maybe someone here can help me.

I have made some code for a wishbone model in VHDL and some procedures
to write and read to it and a
Record to group the signals together and to be able to have more than
one wishbone with the same set of procedures.

I think that there is no problem with the procedure but i am having
problems to pass some parameters.

If i call the procedure with completely constant values it works
perfekt.
If i call it with a signal of the same length, it doesnt give error in
that line. Also if the signal is initialiced with only a constant it
works too.
But i cant find the way to make the parameters non-constant.
I mean, to pass values of possible variables, multiple constants
definitions or even signals.

Please see my chunck of code, where i think the error ist.
If you need more please tell me. I just dont want to polute the post.



signal cpol : std_logic '0';
signal cpha : std_logic '0';
signal e : std_logic_vector(1 downto 0) := "00";

signal d: std_logic_vector(7 downto 0);

signal wishbone0 : wb_master.t_wishbone;

constant SPCR : std_logic_vector(3 downto 0) := "00";


.......


wb_master.bus_write( wishbone0, 1, SPCR, (B"0101", cpol, cpha,
e) ); <------- ERROR here


..... or .....


d <= "01010000";
d(3) <= cpol; <------- ERROR here
d(2) <= cpha; <------- ERROR here
d(1 downto 0) <= e; <------- ERROR here
wb_master.bus_write( wishbone0, 1, SPCR, d );


ERROR is:

Target type ieee.std_logic_1164.std_ulogic in signal assignment is
different frim expression type std.standard.integer.
Target type ieee.std_logic_1164.std_ulogic in signal assignment is
different frim expression type std.standard.integer.
Target type ieee.std_logic_1164.std_ulogic in signal assignment is
different frim expression type std.standard.integer.

(one for each marked line)

..... where inside a package : ....

procedure bus_write (
signal wb : inout t_wishbone ;
delay : in natural ;
a : in std_logic_vector (1 down to 0) ;
d : in std_logic_vector(7 downto 0)
) is ....




Thank you very much.
Diego

 

[Diego UTN-FRP]

Thank you very much, but now it gives other errors:

When i assign d <= B"0101" & cpol & cpha & e;

No feasible entries for infix operator "&".
Bad expression in left operand of infix expression "&".
Bad expression in left operand of infix expression "&".
Type error resolving infix expression "&" as type
ieee.std_logic_1164.std_logic_vector

When i directly use it in bus_write()

No feasible entries for infix operator "&".
Bad expression in left operand of infix expression "&".
Bad expression in left operand of infix expression "&".



I am not use to the language and so, to this kind of error messages
which are not very descriptive to me.

I also tryed with some other changes, like concatenate only cpol, cpha
and e without the constant and didnt work, and to delcare cpol and
cpha and e of the same vector type, but also didnt work.

I would apreciate more help.
Cheers.
Diego

 

[KJ]

Hello people.

Please see my chunck of code, where i think the error ist.
If you need more please tell me. I just dont want to polute the post.

I think you may need to 'pollute the post', because what you've posted
does not match what you say is in your code.

The code you posted is...

d <= "01010000";
d(3) <= cpol; <------- ERROR here
d(2) <= cpha; <------- ERROR here
d(1 downto 0) <= e; <------- ERROR here

The error you posted is...

ERROR is:

Target type ieee.std_logic_1164.std_ulogic in signal assignment is
different frim expression type std.standard.integer.
Target type ieee.std_logic_1164.std_ulogic in signal assignment is
different frim expression type std.standard.integer.
Target type ieee.std_logic_1164.std_ulogic in signal assignment is
different frim expression type std.standard.integer.

What the error is saying is that the target (in this case, various
bits of signal 'd' which is defined as a std_logic_vector) is
different from the expression (which is the right hand side of the
assignment). On your three assignments, the expressions are
'cpol'
'cpha'
'e'

Each of these expressions are defined in your signal defs as std_logic
or std_logic_vector. But the error that you posted is that the
compiler is complaining because the expression is not of type
'std.standard.integer'. This means that when analyzing the code, it
thought each of the expressions (i.e. 'cpol', 'cpha' and 'e') was of
type integer. From that one can conclude one of the following
problems...
- Your posted code snippets is not what is producing the posted errors
- Your tool is deficient

Kevin Jennings

 

[HT-Lab]

On Fri, 27 Nov 2009 10:38:21 -0800 (PST), Diego UTN-FRP wrote:
until you
have learnt more about operator overloading and VHDL's
wonderfully flexible data type system.

Stick with it; it's worth the effort

I just noticed your new signature, I hope Verilab can give you the same language
challenges that Doulos gave you although not many verification companies use
VHDL nowadays :-(

Good luck in your new job,

Hans
www.ht-lab.com

 

[Diego UTN-FRP]

First. Thanks to all for your help.
Second. Sadly it was true, that the second problem was in a code that
i didnt posted. I have recently realised that.

The problematic code is:


for cpol in 0 to 1 loop
for cpha in 0 to 1 loop
for e in 0 to 3 loop
-- load control register
d(7 downto 0) <= "0101" & cpol & cpha & e;
wb_master.bus_write( wishbone0, 1, SPCR, d ); ---(B"0101",
cpol, cpha, e)
-- verify control register
wb_master.cmp ( wishbone0, 0, SPCR, "0101" & cpol & cpha &
e );

-- load extended control register
wb_master.bus_write( wishbone0, 1,SPER, (others=>'0') );
-- verify extended control register
wb_master.cmp ( wishbone0, 0,SPER, (others=>'0'));

-- make TESTS loading data register and checking back
wb_master.bus_write( wishbone0, 1, SPDR, B"10111100");
wb_master.cmp ( wishbone0, 0, SPDR, B"10111100");
.......


Notice the 3 for loop. The variable names were meant to increment
thoose variables. Wrong of course and thats why it was taken as an
integer, so i changed the names to something else, undeclared, and
everything worked like a charm. Concatenation now doesnt gives any
error.




Thanks to all.
Diego