TestBench in VHDL code

[ducatired]

Hello, I've this VHDL code. Now I would try if it work well. Can you help me to made testbench of this code? Many thanks.


library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity DAC is

Port (
DACin : in STD_LOGIC_VECTOR(7 downto 0); -- DACin a 8 bits
Clk : in STD_LOGIC; -- Clock (fronte di salita)
Reset : in STD_LOGIC; -- Il Reset e' attivo ALTO
DACout : out STD_LOGIC
);
end DAC;

architecture DAC_SigmaDelta of DAC is

signal DeltaAdder : STD_LOGIC_VECTOR(9 downto 0) ;
signal SigmaAdder : STD_LOGIC_VECTOR(9 downto 0) ;
signal SigmaLatch : STD_LOGIC_VECTOR(9 downto 0) ;
signal DeltaB : STD_LOGIC_VECTOR(9 downto 0) ;
signal DACin_10bits : STD_LOGIC_VECTOR(9 downto 0) ;



begin

DeltaB <= SigmaLatch(9) & SigmaLatch(9) & "00000000";
DACin_10bits <= ("00" & DACin);


process (DACin_10bits, DeltaB)
begin
DeltaAdder <= DACin_10bits + DeltaB;
end process;


process (DeltaAdder, SigmaLatch)
begin
SigmaAdder <= DeltaAdder + SigmaLatch;
end process;


process(reset, Clk, SigmaAdder)
begin

if(reset='1') then

SigmaLatch <= (others => '0');


elsif (Clk'event and Clk = '1') then

SigmaLatch <= SigmaAdder;

end if;
end process;



process(reset, Clk)
begin
if(reset = '1') then

DACout <= '0';

else

-- fronte di salita:
if(Clk'event and Clk = '1') then

DACOut <= SigmaLatch(9);

end if;
end if;
end process;

end DAC_SigmaDelta;