B
BLF
I am using Aldec 7.1. I wrote a testbench and was able to view the
input and output signals as called out in the Entity of the design
until I wanted to view an internal signal.
My question is how do I view the internal signals such as the
"next_state" of a state machine in the design?
Do I have to assign them to a port in order to view them when I run
the testbench. I.E "Buffered_State <= Next_State;" ????
entity Detection is
port (
.
.
.
Buffered_State : out std_logic_vector;
.
.
);
end Detection;
architecture RTL of Detection is
begin
state_clockedrocess(clk) begin
if rising_edge(clk) then
state <= next_state;
end if;
end process state_clocked;
.
.
.
----------------------------------------------------------------
case statements
---------------------------------------------------------------.
.
.
.
buffered_state <= next_state;
.
.
.
end RTL;
However if I rewrite the code to output the "states" to an "out" port,
I get the error message:
Assignment target incompatible with right side. Expected type
"std_logic_vector".
I can understand the reason why it says this since the "type" is
"StateType" for the signal "next_state".
So once again, How do I go about viewing this internal signal?
input and output signals as called out in the Entity of the design
until I wanted to view an internal signal.
My question is how do I view the internal signals such as the
"next_state" of a state machine in the design?
Do I have to assign them to a port in order to view them when I run
the testbench. I.E "Buffered_State <= Next_State;" ????
entity Detection is
port (
.
.
.
Buffered_State : out std_logic_vector;
.
.
);
end Detection;
architecture RTL of Detection is
begin
state_clockedrocess(clk) begin
if rising_edge(clk) then
state <= next_state;
end if;
end process state_clocked;
.
.
.
----------------------------------------------------------------
case statements
---------------------------------------------------------------.
.
.
.
buffered_state <= next_state;
.
.
.
end RTL;
However if I rewrite the code to output the "states" to an "out" port,
I get the error message:
Assignment target incompatible with right side. Expected type
"std_logic_vector".
I can understand the reason why it says this since the "type" is
"StateType" for the signal "next_state".
So once again, How do I go about viewing this internal signal?