TimingAnalyzer -- Build Timing Diagrams directly from VHDL orVerilog

[timinganalyzer]

Hi All,

The latest version of the program is beta version 0.945. Python
scripting, improved GUI zooming, and logic function simulations have
been the focus in the 0.94X series

An application note on the website shows how to automatically generate
timing diagrams directly from vhdl. Using file I/O from VHDL or any
RTL, you output text files that are python scripts that the
TimingAnalyzer executes to build timing diagrams from simulations.
One use is automatically generating 100s of timing of timing diagrams
from simulations for documentation purposes.

Also, I hope you know that the program is now freeWare so this is not
a marketing or sales message but just a message to keep others in our
business informed about new features. As always, user feedback is
welcome and your opinions and suggestions are shaping the look and
feel of the program.

You can see a list of all the changes at
http://www.timing-diagrams.com/dokuwiki/doku.php?id=download

Thank you,
Dan Fabrizio
www.timing-diagrams.com

 

[Gabor]

Hi All,

The latest version of the program is beta version 0.945.  Python
scripting,  improved GUI zooming, and logic function simulations have
been the focus in the 0.94X series

An application note on the website shows how to automatically generate
timing diagrams directly from vhdl. Using file I/O from VHDL or any
RTL,  you output text files that are python scripts that the
TimingAnalyzer executes to build timing diagrams from simulations.
One use is automatically generating 100s of timing of timing diagrams
from simulations for documentation purposes.

Also,  I hope you know that the program is now freeWare so this is not
a marketing or sales message but just a message to keep others in our
business informed about new features.  As always,  user feedback is
welcome and your opinions and suggestions are shaping the look and
feel of the program.

You can see a list of all the changes athttp://www.timing-diagrams.com/dokuwiki/doku.php?id=download

Thank you,
Dan Fabriziowww.timing-diagrams.com

Very cool. Please give another post when the Verilog example is
available.

Regards,
Gabor