tool for graphical scematic design entry?

[streita]

Hi all,

i'am now allmost 3 years in asic development was using visual elite
from summit for design entry. the problem is that the database is
binary and you are dependend on that tool. now im really interested in
some graphical schemetic entry tool just for creating hirarchical block
diagrams and with posibillity of interconnecting that blocks. Parallel
i wish to have a window with the created framework source code that i
can extend. If i add ports in the source window the graphical window
should recognise that and add the port in the schematic.
That feature forward and backward compatibility i.e. from source to
graphic and visa versa i know from the software development tool
"together". there you can create class diagramms graphically. parallel
you have the source window and if you add methods or members the
graphic will update imediatly.

does any one know a standalone graphical entry tool that creates vhdl
source coade and with a visa versa update functionality?

Andreas

 

[Mike Treseler]

i'am now allmost 3 years in asic development was using visual elite
from summit for design entry. the problem is that the database is
binary and you are dependend on that tool.

The only way to eliminate this problem is to
use text as your source format.

now im really interested in
some graphical schemetic entry tool just for creating hirarchical block
diagrams and with posibillity of interconnecting that blocks. Parallel
i wish to have a window with the created framework source code that i
can extend.

Emacs vhdl-mode provides port and compose operations
that can automate the pasting and "wiring" up design
blocks using only text.

If i add ports in the source window the graphical window
should recognise that and add the port in the schematic.

Most synthesis programs can draw block diagrams
from the finished code.

does any one know a standalone graphical entry tool that creates vhdl
source coade and with a visa versa update functionality?

The graphical editors for VHDL that I have
evaluated generate ugly code in one direction
and are very fussy about the other direction.
Consider editing text and letting the computer
draw the diagrams.

-- Mike Treseler